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Ip=[199.43.4.28]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR07MB6964 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-19_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906190072 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch replace phylib API's by phylink API's. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/Kconfig | 2 +- drivers/net/ethernet/cadence/macb.h | 3 + drivers/net/ethernet/cadence/macb_main.c | 312 +++++++++++++---------- 3 files changed, 182 insertions(+), 135 deletions(-) diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig index 1766697c9c5a..d71411a71587 100644 --- a/drivers/net/ethernet/cadence/Kconfig +++ b/drivers/net/ethernet/cadence/Kconfig @@ -22,7 +22,7 @@ if NET_VENDOR_CADENCE config MACB tristate "Cadence MACB/GEM support" depends on HAS_DMA - select PHYLIB + select PHYLINK ---help--- The Cadence MACB ethernet interface is found on many Atmel AT32 and AT91 parts. This driver also supports the Cadence GEM (Gigabit diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 00ee5e8e0ff0..35ed13236c8b 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -14,6 +14,7 @@ #include #include #include +#include #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) #define MACB_EXT_DESC @@ -1227,6 +1228,8 @@ struct macb { u32 rx_intr_mask; struct macb_pm_data pm_data; + struct phylink *pl; + struct phylink_config pl_config; }; #ifdef CONFIG_MACB_USE_HWSTAMP diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index c545c5b435d8..830af86d3c65 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -39,6 +39,7 @@ #include #include #include +#include #include "macb.h" /* This structure is only used for MACB on SiFive FU540 devices */ @@ -438,115 +439,150 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) netdev_err(dev, "adjusting tx_clk failed.\n"); } -static void macb_handle_link_change(struct net_device *dev) +static void gem_phylink_validate(struct phylink_config *pl_config, + unsigned long *supported, + struct phylink_link_state *state) { - struct macb *bp = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - unsigned long flags; - int status_change = 0; + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + switch (state->interface) { + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) { + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 1000baseT_Half); + } + } + /* fallthrough */ + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + break; + default: + break; + } - spin_lock_irqsave(&bp->lock, flags); + bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} - if (phydev->link) { - if ((bp->speed != phydev->speed) || - (bp->duplex != phydev->duplex)) { - u32 reg; +static int gem_phylink_mac_link_state(struct phylink_config *pl_config, + struct phylink_link_state *state) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); - reg = macb_readl(bp, NCFGR); - reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (macb_is_gem(bp)) - reg &= ~GEM_BIT(GBE); + state->speed = bp->speed; + state->duplex = bp->duplex; + state->link = bp->link; + return 1; +} - if (phydev->duplex) - reg |= MACB_BIT(FD); - if (phydev->speed == SPEED_100) - reg |= MACB_BIT(SPD); - if (phydev->speed == SPEED_1000 && - bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) - reg |= GEM_BIT(GBE); +static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, + const struct phylink_link_state *state) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + unsigned long flags; - macb_or_gem_writel(bp, NCFGR, reg); + spin_lock_irqsave(&bp->lock, flags); - bp->speed = phydev->speed; - bp->duplex = phydev->duplex; - status_change = 1; - } - } + if (bp->speed != state->speed || + bp->duplex != state->duplex) { + u32 reg; - if (phydev->link != bp->link) { - if (!phydev->link) { - bp->speed = 0; - bp->duplex = -1; + reg = macb_readl(bp, NCFGR); + reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (macb_is_gem(bp)) + reg &= ~GEM_BIT(GBE); + if (state->duplex) + reg |= MACB_BIT(FD); + + switch (state->speed) { + case SPEED_1000: + reg |= GEM_BIT(GBE); + break; + case SPEED_100: + reg |= MACB_BIT(SPD); + break; + default: + break; } - bp->link = phydev->link; + macb_or_gem_writel(bp, NCFGR, reg); + + bp->speed = state->speed; + bp->duplex = state->duplex; - status_change = 1; + if (state->link) + macb_set_tx_clk(bp->tx_clk, state->speed, netdev); } spin_unlock_irqrestore(&bp->lock, flags); +} - if (status_change) { - if (phydev->link) { - /* Update the TX clock rate if and only if the link is - * up and there has been a link change. - */ - macb_set_tx_clk(bp->tx_clk, phydev->speed, dev); +static void gem_mac_link_up(struct phylink_config *pl_config, unsigned int mode, + phy_interface_t interface, struct phy_device *phy) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); - netif_carrier_on(dev); - netdev_info(dev, "link up (%d/%s)\n", - phydev->speed, - phydev->duplex == DUPLEX_FULL ? - "Full" : "Half"); - } else { - netif_carrier_off(dev); - netdev_info(dev, "link down\n"); - } - } + bp->link = 1; + /* Enable TX and RX */ + macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); +} + +static void gem_mac_link_down(struct phylink_config *pl_config, + unsigned int mode, phy_interface_t interface) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + + bp->link = 0; + /* Disable TX and RX */ + macb_writel(bp, NCR, + macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE))); } +static const struct phylink_mac_ops gem_phylink_ops = { + .validate = gem_phylink_validate, + .mac_link_state = gem_phylink_mac_link_state, + .mac_config = gem_mac_config, + .mac_link_up = gem_mac_link_up, + .mac_link_down = gem_mac_link_down, +}; + /* based on au1000_eth. c*/ static int macb_mii_probe(struct net_device *dev) { struct macb *bp = netdev_priv(dev); struct phy_device *phydev; struct device_node *np; - int ret, i; + int ret; np = bp->pdev->dev.of_node; ret = 0; - if (np) { - if (of_phy_is_fixed_link(np)) { - bp->phy_node = of_node_get(np); - } else { - bp->phy_node = of_parse_phandle(np, "phy-handle", 0); - /* fallback to standard phy registration if no - * phy-handle was found nor any phy found during - * dt phy registration - */ - if (!bp->phy_node && !phy_find_first(bp->mii_bus)) { - for (i = 0; i < PHY_MAX_ADDR; i++) { - phydev = mdiobus_scan(bp->mii_bus, i); - if (IS_ERR(phydev) && - PTR_ERR(phydev) != -ENODEV) { - ret = PTR_ERR(phydev); - break; - } - } - - if (ret) - return -ENODEV; - } - } + bp->pl_config.dev = &dev->dev; + bp->pl_config.type = PHYLINK_NETDEV; + bp->pl = phylink_create(&bp->pl_config, of_fwnode_handle(np), + bp->phy_interface, &gem_phylink_ops); + if (IS_ERR(bp->pl)) { + netdev_err(dev, + "error creating PHYLINK: %ld\n", PTR_ERR(bp->pl)); + return PTR_ERR(bp->pl); } - if (bp->phy_node) { - phydev = of_phy_connect(dev, bp->phy_node, - &macb_handle_link_change, 0, - bp->phy_interface); - if (!phydev) - return -ENODEV; - } else { + ret = phylink_of_phy_connect(bp->pl, np, 0); + if (ret == -ENODEV && bp->mii_bus) { phydev = phy_find_first(bp->mii_bus); if (!phydev) { netdev_err(dev, "no PHY found\n"); @@ -554,29 +590,18 @@ static int macb_mii_probe(struct net_device *dev) } /* attach the mac to the phy */ - ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, - bp->phy_interface); + ret = phylink_connect_phy(bp->pl, phydev); if (ret) { netdev_err(dev, "Could not attach to PHY\n"); return ret; } } - /* mask with MAC supported features */ - if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) - phy_set_max_speed(phydev, SPEED_1000); - else - phy_set_max_speed(phydev, SPEED_100); - - if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF) - phy_remove_link_mode(phydev, - ETHTOOL_LINK_MODE_1000baseT_Half_BIT); - bp->link = 0; bp->speed = 0; bp->duplex = -1; - return 0; + return ret; } static int macb_mii_init(struct macb *bp) @@ -604,17 +629,7 @@ static int macb_mii_init(struct macb *bp) dev_set_drvdata(&bp->dev->dev, bp->mii_bus); np = bp->pdev->dev.of_node; - if (np && of_phy_is_fixed_link(np)) { - if (of_phy_register_fixed_link(np) < 0) { - dev_err(&bp->pdev->dev, - "broken fixed-link specification %pOF\n", np); - goto err_out_free_mdiobus; - } - - err = mdiobus_register(bp->mii_bus); - } else { - err = of_mdiobus_register(bp->mii_bus, np); - } + err = of_mdiobus_register(bp->mii_bus, np); if (err) goto err_out_free_fixed_link; @@ -630,7 +645,6 @@ static int macb_mii_init(struct macb *bp) err_out_free_fixed_link: if (np && of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); -err_out_free_mdiobus: of_node_put(bp->phy_node); mdiobus_free(bp->mii_bus); err_out: @@ -2422,7 +2436,7 @@ static int macb_open(struct net_device *dev) netif_carrier_off(dev); /* if the phy is not yet register, retry later*/ - if (!dev->phydev) { + if (!bp->pl) { err = -EAGAIN; goto pm_exit; } @@ -2444,7 +2458,7 @@ static int macb_open(struct net_device *dev) macb_init_hw(bp); /* schedule a link state check */ - phy_start(dev->phydev); + phylink_start(bp->pl); netif_tx_start_all_queues(dev); @@ -2471,8 +2485,8 @@ static int macb_close(struct net_device *dev) for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) napi_disable(&queue->napi); - if (dev->phydev) - phy_stop(dev->phydev); + if (bp->pl) + phylink_stop(bp->pl); spin_lock_irqsave(&bp->lock, flags); macb_reset_hw(bp); @@ -3161,6 +3175,29 @@ static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) return ret; } +static int gem_ethtool_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *cmd) +{ + struct macb *bp = netdev_priv(netdev); + + if (!bp->pl) + return -ENOTSUPP; + + return phylink_ethtool_ksettings_get(bp->pl, cmd); +} + +static int +gem_ethtool_set_link_ksettings(struct net_device *netdev, + const struct ethtool_link_ksettings *cmd) +{ + struct macb *bp = netdev_priv(netdev); + + if (!bp->pl) + return -ENOTSUPP; + + return phylink_ethtool_ksettings_set(bp->pl, cmd); +} + static const struct ethtool_ops macb_ethtool_ops = { .get_regs_len = macb_get_regs_len, .get_regs = macb_get_regs, @@ -3168,8 +3205,8 @@ static const struct ethtool_ops macb_ethtool_ops = { .get_ts_info = ethtool_op_get_ts_info, .get_wol = macb_get_wol, .set_wol = macb_set_wol, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_link_ksettings = gem_ethtool_get_link_ksettings, + .set_link_ksettings = gem_ethtool_set_link_ksettings, .get_ringparam = macb_get_ringparam, .set_ringparam = macb_set_ringparam, }; @@ -3182,8 +3219,8 @@ static const struct ethtool_ops gem_ethtool_ops = { .get_ethtool_stats = gem_get_ethtool_stats, .get_strings = gem_get_ethtool_strings, .get_sset_count = gem_get_sset_count, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_link_ksettings = gem_ethtool_get_link_ksettings, + .set_link_ksettings = gem_ethtool_set_link_ksettings, .get_ringparam = macb_get_ringparam, .set_ringparam = macb_set_ringparam, .get_rxnfc = gem_get_rxnfc, @@ -3192,17 +3229,16 @@ static const struct ethtool_ops gem_ethtool_ops = { static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { - struct phy_device *phydev = dev->phydev; struct macb *bp = netdev_priv(dev); if (!netif_running(dev)) return -EINVAL; - if (!phydev) + if (!bp->pl) return -ENODEV; if (!bp->ptp_info) - return phy_mii_ioctl(phydev, rq, cmd); + return phylink_mii_ioctl(bp->pl, rq, cmd); switch (cmd) { case SIOCSHWTSTAMP: @@ -3210,7 +3246,7 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) case SIOCGHWTSTAMP: return bp->ptp_info->get_hwtst(dev, rq); default: - return phy_mii_ioctl(phydev, rq, cmd); + return phylink_mii_ioctl(bp->pl, rq, cmd); } } @@ -3710,7 +3746,7 @@ static int at91ether_open(struct net_device *dev) MACB_BIT(HRESP)); /* schedule a link state check */ - phy_start(dev->phydev); + phylink_start(lp->pl); netif_start_queue(dev); @@ -4183,13 +4219,12 @@ static int macb_probe(struct platform_device *pdev) struct clk *tsu_clk = NULL; unsigned int queue_mask, num_queues; bool native_io; - struct phy_device *phydev; struct net_device *dev; struct resource *regs; void __iomem *mem; const char *mac; struct macb *bp; - int err, val; + int err, val, phy_mode; regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); mem = devm_ioremap_resource(&pdev->dev, regs); @@ -4310,12 +4345,12 @@ static int macb_probe(struct platform_device *pdev) macb_get_hwaddr(bp); } - err = of_get_phy_mode(np); - if (err < 0) + phy_mode = of_get_phy_mode(np); + if (phy_mode < 0) /* not found in DT, MII by default */ bp->phy_interface = PHY_INTERFACE_MODE_MII; else - bp->phy_interface = err; + bp->phy_interface = phy_mode; /* IP specific init */ err = init(pdev); @@ -4326,8 +4361,6 @@ static int macb_probe(struct platform_device *pdev) if (err) goto err_out_free_netdev; - phydev = dev->phydev; - netif_carrier_off(dev); err = register_netdev(dev); @@ -4339,7 +4372,8 @@ static int macb_probe(struct platform_device *pdev) tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task, (unsigned long)bp); - phy_attached_info(phydev); + if (dev->phydev) + phy_attached_info(dev->phydev); netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), @@ -4351,7 +4385,9 @@ static int macb_probe(struct platform_device *pdev) return 0; err_out_unregister_mdio: - phy_disconnect(dev->phydev); + rtnl_lock(); + phylink_disconnect_phy(bp->pl); + rtnl_unlock(); mdiobus_unregister(bp->mii_bus); of_node_put(bp->phy_node); if (np && of_phy_is_fixed_link(np)) @@ -4385,13 +4421,18 @@ static int macb_remove(struct platform_device *pdev) if (dev) { bp = netdev_priv(dev); - if (dev->phydev) - phy_disconnect(dev->phydev); + if (bp->pl) { + rtnl_lock(); + phylink_disconnect_phy(bp->pl); + rtnl_unlock(); + } mdiobus_unregister(bp->mii_bus); if (np && of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); dev->phydev = NULL; mdiobus_free(bp->mii_bus); + if (bp->pl) + phylink_destroy(bp->pl); unregister_netdev(dev); pm_runtime_disable(&pdev->dev); @@ -4434,8 +4475,9 @@ static int __maybe_unused macb_suspend(struct device *dev) for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) napi_disable(&queue->napi); - phy_stop(netdev->phydev); - phy_suspend(netdev->phydev); + phylink_stop(bp->pl); + if (netdev->phydev) + phy_suspend(netdev->phydev); spin_lock_irqsave(&bp->lock, flags); macb_reset_hw(bp); spin_unlock_irqrestore(&bp->lock, flags); @@ -4483,9 +4525,11 @@ static int __maybe_unused macb_resume(struct device *dev) for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) napi_enable(&queue->napi); - phy_resume(netdev->phydev); - phy_init_hw(netdev->phydev); - phy_start(netdev->phydev); + if (netdev->phydev) { + phy_resume(netdev->phydev); + phy_init_hw(netdev->phydev); + } + phylink_start(bp->pl); } bp->macbgem_ops.mog_init_rings(bp); From patchwork Wed Jun 19 08:40:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1118546 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6827 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-19_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906190072 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch add support for SGMII interface) and 2.5Gbps MAC in Cadence ethernet controller driver. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 76 ++++++++++-- drivers/net/ethernet/cadence/macb_main.c | 151 ++++++++++++++++++++--- 2 files changed, 200 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 35ed13236c8b..d7ffbfb2ecc0 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -80,6 +80,7 @@ #define MACB_RBQPH 0x04D4 /* GEM register offsets. */ +#define GEM_NCR 0x0000 /* Network Control */ #define GEM_NCFGR 0x0004 /* Network Config */ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ @@ -159,6 +160,9 @@ #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ +#define GEM_PCS_CTRL 0x0200 /* PCS Control */ +#define GEM_PCS_STATUS 0x0204 /* PCS Status */ +#define GEM_PCS_AN_LP_BASE 0x0214 /* PCS AN LP BASE*/ #define GEM_DCFG1 0x0280 /* Design Config 1 */ #define GEM_DCFG2 0x0284 /* Design Config 2 */ #define GEM_DCFG3 0x0288 /* Design Config 3 */ @@ -274,6 +278,10 @@ #define MACB_IRXFCS_OFFSET 19 #define MACB_IRXFCS_SIZE 1 +/* GEM specific NCR bitfields. */ +#define GEM_TWO_PT_FIVE_GIG_OFFSET 29 +#define GEM_TWO_PT_FIVE_GIG_SIZE 1 + /* GEM specific NCFGR bitfields. */ #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ #define GEM_GBE_SIZE 1 @@ -326,6 +334,9 @@ #define MACB_MDIO_SIZE 1 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ #define MACB_IDLE_SIZE 1 +#define MACB_DUPLEX_OFFSET 3 +#define MACB_DUPLEX_SIZE 1 + /* Bitfields in TSR */ #define MACB_UBR_OFFSET 0 /* Used bit read */ @@ -459,11 +470,37 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfields in PCS_CONTROL. */ +#define GEM_PCS_CTRL_RST_OFFSET 15 +#define GEM_PCS_CTRL_RST_SIZE 1 +#define GEM_PCS_CTRL_EN_AN_OFFSET 12 +#define GEM_PCS_CTRL_EN_AN_SIZE 1 +#define GEM_PCS_CTRL_RESTART_AN_OFFSET 9 +#define GEM_PCS_CTRL_RESTART_AN_SIZE 1 + +/* Bitfields in PCS_STATUS. */ +#define GEM_PCS_STATUS_AN_DONE_OFFSET 5 +#define GEM_PCS_STATUS_AN_DONE_SIZE 1 +#define GEM_PCS_STATUS_AN_SUPPORT_OFFSET 3 +#define GEM_PCS_STATUS_AN_SUPPORT_SIZE 1 +#define GEM_PCS_STATUS_LINK_OFFSET 2 +#define GEM_PCS_STATUS_LINK_SIZE 1 + +/* Bitfield in PCS_AN_LP_BASE */ +#define GEM_PCS_AN_LP_BASE_LINK_OFFSET 15 +#define GEM_PCS_AN_LP_BASE_LINK_SIZE 1 +#define GEM_PCS_AN_LP_BASE_DUPLEX_OFFSET 12 +#define GEM_PCS_AN_LP_BASE_DUPLEX_SIZE 1 +#define GEM_PCS_AN_LP_BASE_SPEED_OFFSET 10 +#define GEM_PCS_AN_LP_BASE_SPEED_SIZE 2 + /* Bitfields in DCFG1. */ #define GEM_IRQCOR_OFFSET 23 #define GEM_IRQCOR_SIZE 1 #define GEM_DBWDEF_OFFSET 25 #define GEM_DBWDEF_SIZE 3 +#define GEM_NO_PCS_OFFSET 0 +#define GEM_NO_PCS_SIZE 1 /* Bitfields in DCFG2. */ #define GEM_RX_PKT_BUFF_OFFSET 20 @@ -636,19 +673,32 @@ #define MACB_MAN_CODE 2 /* Capability mask bits */ -#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 -#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 -#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 -#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 -#define MACB_CAPS_USRIO_DISABLED 0x00000010 -#define MACB_CAPS_JUMBO 0x00000020 -#define MACB_CAPS_GEM_HAS_PTP 0x00000040 -#define MACB_CAPS_BD_RD_PREFETCH 0x00000080 -#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 -#define MACB_CAPS_FIFO_MODE 0x10000000 -#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 -#define MACB_CAPS_SG_DISABLED 0x40000000 -#define MACB_CAPS_MACB_IS_GEM 0x80000000 +#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0) +#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1) +#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2) +#define MACB_CAPS_NO_GIGABIT_HALF BIT(3) +#define MACB_CAPS_USRIO_DISABLED BIT(4) +#define MACB_CAPS_JUMBO BIT(5) +#define MACB_CAPS_GEM_HAS_PTP BIT(6) +#define MACB_CAPS_BD_RD_PREFETCH BIT(7) +#define MACB_CAPS_NEEDS_RSTONUBR BIT(8) +#define MACB_CAPS_FIFO_MODE BIT(28) +#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29) +#define MACB_CAPS_SG_DISABLED BIT(30) +#define MACB_CAPS_MACB_IS_GEM BIT(31) +#define MACB_CAPS_PCS BIT(24) +#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25) + +#define MACB_GEM7010_IDNUM 0x009 +#define MACB_GEM7014_IDNU 0x107 +#define MACB_GEM7014A_IDNUM 0x207 +#define MACB_GEM7016_IDNUM 0x10a +#define MACB_GEM7017_IDNUM 0x00a +#define MACB_GEM7017A_IDNUM 0x20a +#define MACB_GEM7020_IDNUM 0x003 +#define MACB_GEM7021_IDNUM 0x00c +#define MACB_GEM7021A_IDNUM 0x20c +#define MACB_GEM7022_IDNUM 0x00b /* LSO settings */ #define MACB_LSO_UFO_ENABLE 0x01 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 830af86d3c65..884d2a4408ad 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -403,6 +403,7 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, */ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) { + struct macb *bp = netdev_priv(dev); long ferr, rate, rate_rounded; if (!clk) @@ -418,6 +419,12 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) case SPEED_1000: rate = 125000000; break; + case SPEED_2500: + if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) + rate = 312500000; + else + rate = 125000000; + break; default: return; } @@ -448,15 +455,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config, __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) + phylink_set(mask, 2500baseT_Full); + /* fallthrough */ case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII: if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); - if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) { - phylink_set(mask, 1000baseT_Half); + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) phylink_set(mask, 1000baseT_Half); - } } /* fallthrough */ case PHY_INTERFACE_MODE_MII: @@ -466,6 +474,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config, phylink_set(mask, 100baseT_Half); phylink_set(mask, 100baseT_Full); break; + + case PHY_INTERFACE_MODE_2500BASEX: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) + phylink_set(mask, 2500baseX_Full); + /* fallthrough */ + case PHY_INTERFACE_MODE_1000BASEX: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) + phylink_set(mask, 1000baseX_Full); + break; + default: break; } @@ -480,13 +498,52 @@ static int gem_phylink_mac_link_state(struct phylink_config *pl_config, { struct net_device *netdev = to_net_dev(pl_config->dev); struct macb *bp = netdev_priv(netdev); + u32 status; - state->speed = bp->speed; - state->duplex = bp->duplex; - state->link = bp->link; + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { + status = gem_readl(bp, PCS_STATUS); + state->an_complete = GEM_BFEXT(PCS_STATUS_AN_DONE, status); + status = gem_readl(bp, PCS_AN_LP_BASE); + switch (GEM_BFEXT(PCS_AN_LP_BASE_SPEED, status)) { + case 0: + state->speed = SPEED_10; + break; + case 1: + state->speed = SPEED_100; + break; + case 2: + state->speed = SPEED_1000; + break; + default: + break; + } + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR)); + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR)); + } else if (bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + state->speed = SPEED_2500; + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR)); + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR)); + } else if (bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { + state->speed = SPEED_1000; + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR)); + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR)); + } return 1; } +static void gem_mac_an_restart(struct phylink_config *pl_config) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_RESTART_AN)); + } +} + static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, const struct phylink_link_state *state) { @@ -506,18 +563,26 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, reg &= ~GEM_BIT(GBE); if (state->duplex) reg |= MACB_BIT(FD); + macb_or_gem_writel(bp, NCFGR, reg); switch (state->speed) { + case SPEED_2500: + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) | + gem_readl(bp, NCR)); + break; case SPEED_1000: - reg |= GEM_BIT(GBE); + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); break; case SPEED_100: - reg |= MACB_BIT(SPD); + macb_writel(bp, NCFGR, MACB_BIT(SPD) | + macb_readl(bp, NCFGR)); break; default: break; } - macb_or_gem_writel(bp, NCFGR, reg); bp->speed = state->speed; bp->duplex = state->duplex; @@ -555,6 +620,7 @@ static void gem_mac_link_down(struct phylink_config *pl_config, static const struct phylink_mac_ops gem_phylink_ops = { .validate = gem_phylink_validate, .mac_link_state = gem_phylink_mac_link_state, + .mac_an_restart = gem_mac_an_restart, .mac_config = gem_mac_config, .mac_link_up = gem_mac_link_up, .mac_link_down = gem_mac_link_down, @@ -2248,7 +2314,9 @@ static void macb_init_hw(struct macb *bp) macb_set_hwaddr(bp); config = macb_mdc_clk_div(bp); - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ config |= MACB_BIT(PAE); /* PAuse Enable */ @@ -2273,6 +2341,17 @@ static void macb_init_hw(struct macb *bp) if (bp->caps & MACB_CAPS_JUMBO) bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + //Enable PCS AN + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_EN_AN)); + //Reset PCS block + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_RST)); + } + macb_configure_dma(bp); /* Initialize TX and RX buffers */ @@ -3364,6 +3443,22 @@ static void macb_configure_caps(struct macb *bp, dcfg = gem_readl(bp, DCFG1); if (GEM_BFEXT(IRQCOR, dcfg) == 0) bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; + if (GEM_BFEXT(NO_PCS, dcfg) == 0) + bp->caps |= MACB_CAPS_PCS; + switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) { + case MACB_GEM7016_IDNUM: + case MACB_GEM7017_IDNUM: + case MACB_GEM7017A_IDNUM: + case MACB_GEM7020_IDNUM: + case MACB_GEM7021_IDNUM: + case MACB_GEM7021A_IDNUM: + case MACB_GEM7022_IDNUM: + bp->caps |= MACB_CAPS_USRIO_DISABLED; + bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL; + break; + default: + break; + } dcfg = gem_readl(bp, DCFG2); if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) bp->caps |= MACB_CAPS_FIFO_MODE; @@ -3652,7 +3747,9 @@ static int macb_init(struct platform_device *pdev) /* Set MII management clock divider */ val = macb_mdc_clk_div(bp); val |= macb_dbw(bp); - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); macb_writel(bp, NCFGR, val); @@ -4346,11 +4443,37 @@ static int macb_probe(struct platform_device *pdev) } phy_mode = of_get_phy_mode(np); - if (phy_mode < 0) + if (phy_mode < 0) { /* not found in DT, MII by default */ bp->phy_interface = PHY_INTERFACE_MODE_MII; - else + } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) { + u32 interface_supported = 1; + + if (phy_mode == PHY_INTERFACE_MODE_SGMII || + phy_mode == PHY_INTERFACE_MODE_1000BASEX || + phy_mode == PHY_INTERFACE_MODE_2500BASEX) { + if (!(bp->caps & MACB_CAPS_PCS)) + interface_supported = 0; + } else if (phy_mode == PHY_INTERFACE_MODE_GMII || + phy_mode == PHY_INTERFACE_MODE_RGMII) { + if (!macb_is_gem(bp)) + interface_supported = 0; + } else if (phy_mode != PHY_INTERFACE_MODE_RMII && + phy_mode != PHY_INTERFACE_MODE_MII) { + /* Add new mode before this */ + interface_supported = 0; + } + + if (!interface_supported) { + netdev_err(dev, "Phy mode %s not supported", + phy_modes(phy_mode)); + goto err_out_free_netdev; + } + bp->phy_interface = phy_mode; + } else { + bp->phy_interface = phy_mode; + } /* IP specific init */ err = init(pdev); From patchwork Wed Jun 19 08:40:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1118547 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="lueOm572"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="Aen9UoJq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45TJMJ5rGCz9s5c for ; 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Ip=[158.140.1.28]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR07MB6961 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-19_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=785 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906190072 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch modify MDIO read/write functions to support communication with C45 PHY. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 15 ++++-- drivers/net/ethernet/cadence/macb_main.c | 61 +++++++++++++++++++----- 2 files changed, 61 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index d7ffbfb2ecc0..34768d35aea1 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -667,10 +667,17 @@ #define GEM_CLK_DIV96 5 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_C22_SOF 1 +#define MACB_MAN_C22_WRITE 1 +#define MACB_MAN_C22_READ 2 +#define MACB_MAN_C22_CODE 2 + +#define MACB_MAN_C45_SOF 0 +#define MACB_MAN_C45_ADDR 0 +#define MACB_MAN_C45_WRITE 1 +#define MACB_MAN_C45_POST_READ_INCR 2 +#define MACB_MAN_C45_READ 3 +#define MACB_MAN_C45_CODE 2 /* Capability mask bits */ #define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 884d2a4408ad..cf63381d54ee 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -344,11 +344,30 @@ static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) if (status < 0) goto mdio_read_exit; - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) - | MACB_BF(RW, MACB_MAN_READ) - | MACB_BF(PHYA, mii_id) - | MACB_BF(REGA, regnum) - | MACB_BF(CODE, MACB_MAN_CODE))); + if (regnum & MII_ADDR_C45) { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_ADDR) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(DATA, regnum & 0xFFFF) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + + status = macb_mdio_wait_for_idle(bp); + if (status < 0) + goto mdio_read_exit; + + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_READ) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + } else { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) + | MACB_BF(RW, MACB_MAN_C22_READ) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, regnum) + | MACB_BF(CODE, MACB_MAN_C22_CODE))); + } status = macb_mdio_wait_for_idle(bp); if (status < 0) @@ -377,12 +396,32 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, if (status < 0) goto mdio_write_exit; - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) - | MACB_BF(RW, MACB_MAN_WRITE) - | MACB_BF(PHYA, mii_id) - | MACB_BF(REGA, regnum) - | MACB_BF(CODE, MACB_MAN_CODE) - | MACB_BF(DATA, value))); + if (regnum & MII_ADDR_C45) { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_ADDR) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(DATA, regnum & 0xFFFF) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + + status = macb_mdio_wait_for_idle(bp); + if (status < 0) + goto mdio_write_exit; + + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_WRITE) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(CODE, MACB_MAN_C45_CODE) + | MACB_BF(DATA, value))); + } else { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) + | MACB_BF(RW, MACB_MAN_C22_WRITE) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, regnum) + | MACB_BF(CODE, MACB_MAN_C22_CODE) + | MACB_BF(DATA, value))); + } status = macb_mdio_wait_for_idle(bp); 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Ip=[199.43.4.28]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR07MB6819 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-19_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906190072 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch add support for high speed USXGMII PCS and 10G speed in Cadence ethernet controller driver. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 41 +++++ drivers/net/ethernet/cadence/macb_main.c | 216 +++++++++++++++++++---- 2 files changed, 218 insertions(+), 39 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 34768d35aea1..0910d0bfdceb 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -85,6 +85,7 @@ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ #define GEM_JML 0x0048 /* Jumbo Max Length */ +#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */ #define GEM_HRB 0x0080 /* Hash Bottom */ #define GEM_HRT 0x0084 /* Hash Top */ #define GEM_SA1B 0x0088 /* Specific1 Bottom */ @@ -172,6 +173,9 @@ #define GEM_DCFG7 0x0298 /* Design Config 7 */ #define GEM_DCFG8 0x029C /* Design Config 8 */ #define GEM_DCFG10 0x02A4 /* Design Config 10 */ +#define GEM_DCFG12 0x02AC /* Design Config 12 */ +#define GEM_USX_CONTROL 0x0A80 /* USXGMII control register */ +#define GEM_USX_STATUS 0x0A88 /* USXGMII status register */ #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ @@ -279,6 +283,8 @@ #define MACB_IRXFCS_SIZE 1 /* GEM specific NCR bitfields. */ +#define GEM_ENABLE_HS_MAC_OFFSET 31 +#define GEM_ENABLE_HS_MAC_SIZE 1 #define GEM_TWO_PT_FIVE_GIG_OFFSET 29 #define GEM_TWO_PT_FIVE_GIG_SIZE 1 @@ -470,6 +476,10 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfield in HS_MAC_CONFIG */ +#define GEM_HS_MAC_SPEED_OFFSET 0 +#define GEM_HS_MAC_SPEED_SIZE 3 + /* Bitfields in PCS_CONTROL. */ #define GEM_PCS_CTRL_RST_OFFSET 15 #define GEM_PCS_CTRL_RST_SIZE 1 @@ -535,6 +545,34 @@ #define GEM_RXBD_RDBUFF_OFFSET 8 #define GEM_RXBD_RDBUFF_SIZE 4 +/* Bitfields in DCFG12. */ +#define GEM_HIGH_SPEED_OFFSET 26 +#define GEM_HIGH_SPEED_SIZE 1 + +/* Bitfields in USX_CONTROL. */ +#define GEM_USX_CTRL_SPEED_OFFSET 14 +#define GEM_USX_CTRL_SPEED_SIZE 3 +#define GEM_SERDES_RATE_OFFSET 12 +#define GEM_SERDES_RATE_SIZE 2 +#define GEM_RX_SCR_BYPASS_OFFSET 9 +#define GEM_RX_SCR_BYPASS_SIZE 1 +#define GEM_TX_SCR_BYPASS_OFFSET 8 +#define GEM_TX_SCR_BYPASS_SIZE 1 +#define GEM_RX_SYNC_RESET_OFFSET 2 +#define GEM_RX_SYNC_RESET_SIZE 1 +#define GEM_TX_EN_OFFSET 1 +#define GEM_TX_EN_SIZE 1 +#define GEM_SIGNAL_OK_OFFSET 0 +#define GEM_SIGNAL_OK_SIZE 1 + +/* Bitfields in USX_STATUS. */ +#define GEM_USX_TX_FAULT_OFFSET 28 +#define GEM_USX_TX_FAULT_SIZE 1 +#define GEM_USX_RX_FAULT_OFFSET 27 +#define GEM_USX_RX_FAULT_SIZE 1 +#define GEM_USX_BLOCK_LOCK_OFFSET 0 +#define GEM_USX_BLOCK_LOCK_SIZE 1 + /* Bitfields in TISUBN */ #define GEM_SUBNSINCR_OFFSET 0 #define GEM_SUBNSINCR_SIZE 16 @@ -695,6 +733,7 @@ #define MACB_CAPS_MACB_IS_GEM BIT(31) #define MACB_CAPS_PCS BIT(24) #define MACB_CAPS_MACB_IS_GEM_GXL BIT(25) +#define MACB_CAPS_HIGH_SPEED BIT(26) #define MACB_GEM7010_IDNUM 0x009 #define MACB_GEM7014_IDNU 0x107 @@ -774,6 +813,7 @@ }) #define MACB_READ_NSR(bp) macb_readl(bp, NSR) +#define GEM_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS) /* struct macb_dma_desc - Hardware DMA descriptor * @addr: DMA address of data buffer @@ -1287,6 +1327,7 @@ struct macb { struct macb_pm_data pm_data; struct phylink *pl; struct phylink_config pl_config; + u32 serdes_rate; }; #ifdef CONFIG_MACB_USE_HWSTAMP diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index cf63381d54ee..7b59e64dfe20 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -87,6 +87,20 @@ static struct sifive_fu540_macb_mgmt *mgmt; #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) #define MACB_WOL_ENABLED (0x1 << 1) +enum { + HS_MAC_SPEED_100M, + HS_MAC_SPEED_1000M, + HS_MAC_SPEED_2500M, + HS_MAC_SPEED_5000M, + HS_MAC_SPEED_10000M, + HS_MAC_SPEED_25000M, +}; + +enum { + MACB_SERDES_RATE_5_PT_15625Gbps = 5, + MACB_SERDES_RATE_10_PT_3125Gbps = 10, +}; + /* Graceful stop timeouts in us. We should allow up to * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) */ @@ -96,6 +110,8 @@ static struct sifive_fu540_macb_mgmt *mgmt; #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ +#define MACB_USX_BLOCK_LOCK_TIMEOUT 1000000 /* in usecs */ + /* DMA buffer descriptor might be different size * depends on hardware configuration: * @@ -448,24 +464,37 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) if (!clk) return; - switch (speed) { - case SPEED_10: - rate = 2500000; - break; - case SPEED_100: - rate = 25000000; - break; - case SPEED_1000: - rate = 125000000; - break; - case SPEED_2500: - if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) - rate = 312500000; - else + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + switch (bp->serdes_rate) { + case MACB_SERDES_RATE_5_PT_15625Gbps: + rate = 78125000; + break; + case MACB_SERDES_RATE_10_PT_3125Gbps: + rate = 156250000; + break; + default: + return; + } + } else { + switch (speed) { + case SPEED_10: + rate = 2500000; + break; + case SPEED_100: + rate = 25000000; + break; + case SPEED_1000: rate = 125000000; - break; - default: - return; + break; + case SPEED_2500: + if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) + rate = 312500000; + else + return; + break; + default: + return; + } } rate_rounded = clk_round_rate(clk, rate); @@ -494,6 +523,21 @@ static void gem_phylink_validate(struct phylink_config *pl_config, __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; switch (state->interface) { + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GKR: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { + phylink_set(mask, 10000baseCR_Full); + phylink_set(mask, 10000baseER_Full); + phylink_set(mask, 10000baseKR_Full); + phylink_set(mask, 10000baseLR_Full); + phylink_set(mask, 10000baseLRM_Full); + phylink_set(mask, 10000baseSR_Full); + phylink_set(mask, 10000baseT_Full); + phylink_set(mask, 5000baseT_Full); + phylink_set(mask, 2500baseX_Full); + phylink_set(mask, 1000baseX_Full); + } + /* Fall-through */ case PHY_INTERFACE_MODE_SGMII: if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) phylink_set(mask, 2500baseT_Full); @@ -583,6 +627,63 @@ static void gem_mac_an_restart(struct phylink_config *pl_config) } } +static inline void gem_set_usx_mac_speed(struct macb *bp, int spd) +{ + u32 speed; + + switch (spd) { + case SPEED_10000: + if (bp->serdes_rate >= MACB_SERDES_RATE_10_PT_3125Gbps) { + speed = HS_MAC_SPEED_10000M; + } else { + netdev_warn(bp->dev, "10G speed isn't supported by HW"); + netdev_warn(bp->dev, "Setting speed to 1G"); + speed = HS_MAC_SPEED_1000M; + } + break; + case SPEED_5000: + speed = HS_MAC_SPEED_5000M; + break; + case SPEED_2500: + speed = HS_MAC_SPEED_2500M; + break; + case SPEED_1000: + speed = HS_MAC_SPEED_1000M; + break; + default: + case SPEED_100: + speed = HS_MAC_SPEED_100M; + break; + } + + gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, speed, + gem_readl(bp, HS_MAC_CONFIG))); + gem_writel(bp, USX_CONTROL, GEM_BFINS(USX_CTRL_SPEED, speed, + gem_readl(bp, USX_CONTROL))); +} + +static inline void gem_set_mac_speed(struct macb *bp, int speed) +{ + switch (speed) { + case SPEED_2500: + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) | + gem_readl(bp, NCR)); + break; + case SPEED_1000: + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + break; + case SPEED_100: + macb_writel(bp, NCFGR, MACB_BIT(SPD) | + macb_readl(bp, NCFGR)); + break; + default: + break; + } +} + static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, const struct phylink_link_state *state) { @@ -604,24 +705,10 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, reg |= MACB_BIT(FD); macb_or_gem_writel(bp, NCFGR, reg); - switch (state->speed) { - case SPEED_2500: - gem_writel(bp, NCFGR, GEM_BIT(GBE) | - gem_readl(bp, NCFGR)); - gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) | - gem_readl(bp, NCR)); - break; - case SPEED_1000: - gem_writel(bp, NCFGR, GEM_BIT(GBE) | - gem_readl(bp, NCFGR)); - break; - case SPEED_100: - macb_writel(bp, NCFGR, MACB_BIT(SPD) | - macb_readl(bp, NCFGR)); - break; - default: - break; - } + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) + gem_set_usx_mac_speed(bp, state->speed); + else + gem_set_mac_speed(bp, state->speed); bp->speed = state->speed; bp->duplex = state->duplex; @@ -2342,7 +2429,16 @@ static void macb_configure_dma(struct macb *bp) } } -static void macb_init_hw(struct macb *bp) +static int macb_wait_for_usx_block_lock(struct macb *bp) +{ + u32 val; + + return readx_poll_timeout(GEM_READ_USX_STATUS, bp, val, + val & GEM_BIT(USX_BLOCK_LOCK), + 1, MACB_USX_BLOCK_LOCK_TIMEOUT); +} + +static int macb_init_hw(struct macb *bp) { struct macb_queue *queue; unsigned int q; @@ -2380,6 +2476,23 @@ static void macb_init_hw(struct macb *bp) if (bp->caps & MACB_CAPS_JUMBO) bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + gem_writel(bp, NCR, gem_readl(bp, NCR) | + GEM_BIT(ENABLE_HS_MAC)); + gem_writel(bp, NCFGR, gem_readl(bp, NCFGR) | + MACB_BIT(FD) | GEM_BIT(PCSSEL)); + config = gem_readl(bp, USX_CONTROL); + config = GEM_BFINS(SERDES_RATE, bp->serdes_rate, config); + config &= ~GEM_BIT(TX_SCR_BYPASS); + config &= ~GEM_BIT(RX_SCR_BYPASS); + gem_writel(bp, USX_CONTROL, config | + GEM_BIT(TX_EN)); + config = gem_readl(bp, USX_CONTROL); + gem_writel(bp, USX_CONTROL, config | GEM_BIT(SIGNAL_OK)); + if (macb_wait_for_usx_block_lock(bp) < 0) + return -ETIMEDOUT; + } + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { @@ -2415,6 +2528,7 @@ static void macb_init_hw(struct macb *bp) /* Enable TX and RX */ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); + return 0; } /* The hash address register is 64 bits long and takes up two @@ -2573,7 +2687,9 @@ static int macb_open(struct net_device *dev) napi_enable(&queue->napi); bp->macbgem_ops.mog_init_rings(bp); - macb_init_hw(bp); + err = macb_init_hw(bp); + if (err) + goto init_hw_exit; /* schedule a link state check */ phylink_start(bp->pl); @@ -2583,6 +2699,9 @@ static int macb_open(struct net_device *dev) if (bp->ptp_info) bp->ptp_info->ptp_init(dev); +init_hw_exit: + if (err) + macb_free_consistent(bp); pm_exit: if (err) { pm_runtime_put_sync(&bp->pdev->dev); @@ -3498,6 +3617,9 @@ static void macb_configure_caps(struct macb *bp, default: break; } + dcfg = gem_readl(bp, DCFG12); + if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) + bp->caps |= MACB_CAPS_HIGH_SPEED; dcfg = gem_readl(bp, DCFG2); if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) bp->caps |= MACB_CAPS_FIFO_MODE; @@ -3789,7 +3911,12 @@ static int macb_init(struct platform_device *pdev) if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) - val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); + val |= GEM_BIT(SGMIIEN); + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII || + bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) + val |= GEM_BIT(PCSSEL); macb_writel(bp, NCFGR, val); return 0; @@ -4488,7 +4615,18 @@ static int macb_probe(struct platform_device *pdev) } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) { u32 interface_supported = 1; - if (phy_mode == PHY_INTERFACE_MODE_SGMII || + if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { + if (!(bp->caps & MACB_CAPS_HIGH_SPEED && + bp->caps & MACB_CAPS_PCS)) + interface_supported = 0; + + if (of_property_read_u32(np, "serdes-rate-gbps", + &bp->serdes_rate)) { + netdev_err(dev, + "GEM serdes_rate not specified"); + interface_supported = 0; + } + } else if (phy_mode == PHY_INTERFACE_MODE_SGMII || phy_mode == PHY_INTERFACE_MODE_1000BASEX || phy_mode == PHY_INTERFACE_MODE_2500BASEX) { if (!(bp->caps & MACB_CAPS_PCS)) From patchwork Wed Jun 19 08:41:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1118550 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6972 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-19_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906190072 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org New parameters added to Cadence ethernet controller DT binding for USXGMII interface. Signed-off-by: Parshuram Thombare --- Documentation/devicetree/bindings/net/macb.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 63c73fafe26d..dabdf9d3b574 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -28,6 +28,9 @@ Required properties: Optional elements: 'rx_clk' applies to cdns,zynqmp-gem Optional elements: 'tsu_clk' - clocks: Phandles to input clocks. +- serdes-rate-gbps External serdes rate.Mandatory for USXGMII mode. + 5 - 5G + 10 - 10G The MAC address will be determined using the optional properties defined in ethernet.txt.