From patchwork Thu Nov 2 07:22:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 833243 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ySGmT6msyz9t2l for ; Thu, 2 Nov 2017 18:24:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755161AbdKBHYH convert rfc822-to-8bit (ORCPT ); Thu, 2 Nov 2017 03:24:07 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12490 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755104AbdKBHYE (ORCPT ); Thu, 2 Nov 2017 03:24:04 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 02 Nov 2017 00:23:49 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 02 Nov 2017 00:23:53 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 02 Nov 2017 00:23:53 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 2 Nov 2017 07:22:17 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 2 Nov 2017 07:22:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Thu, 2 Nov 2017 07:22:16 +0000 Received: from vbhadram.nvidia.com (Not Verified[10.19.65.213]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 02 Nov 2017 00:22:16 -0700 From: Bhadram Varka To: CC: , , , Subject: [PATCH] stmmac: use of_property_read_u32 instead of read_u8 Date: Thu, 2 Nov 2017 12:52:13 +0530 Message-ID: <1509607333-8864-1-git-send-email-vbhadram@nvidia.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-NVConfidentiality: public Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Numbers in DT are stored in “cells” which are 32-bits in size. of_property_read_u8 does not work properly because of endianness problem. This causes it to always return 0 with little-endian architectures. Fix it by using of_property_read_u32() OF API. Signed-off-by: Bhadram Varka --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 16 ++++++++-------- include/linux/stmmac.h | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 9e616da..d5efe5b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -161,8 +161,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev, } /* Processing RX queues common config */ - if (of_property_read_u8(rx_node, "snps,rx-queues-to-use", - &plat->rx_queues_to_use)) + if (of_property_read_u32(rx_node, "snps,rx-queues-to-use", + &plat->rx_queues_to_use)) plat->rx_queues_to_use = 1; if (of_property_read_bool(rx_node, "snps,rx-sched-sp")) @@ -184,8 +184,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev, else plat->rx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB; - if (of_property_read_u8(q_node, "snps,map-to-dma-channel", - &plat->rx_queues_cfg[queue].chan)) + if (of_property_read_u32(q_node, "snps,map-to-dma-channel", + &plat->rx_queues_cfg[queue].chan)) plat->rx_queues_cfg[queue].chan = queue; /* TODO: Dynamic mapping to be included in the future */ @@ -215,8 +215,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev, } /* Processing TX queues common config */ - if (of_property_read_u8(tx_node, "snps,tx-queues-to-use", - &plat->tx_queues_to_use)) + if (of_property_read_u32(tx_node, "snps,tx-queues-to-use", + &plat->tx_queues_to_use)) plat->tx_queues_to_use = 1; if (of_property_read_bool(tx_node, "snps,tx-sched-wrr")) @@ -237,8 +237,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev, if (queue >= plat->tx_queues_to_use) break; - if (of_property_read_u8(q_node, "snps,weight", - &plat->tx_queues_cfg[queue].weight)) + if (of_property_read_u32(q_node, "snps,weight", + &plat->tx_queues_cfg[queue].weight)) plat->tx_queues_cfg[queue].weight = 0x10 + queue; if (of_property_read_bool(q_node, "snps,dcb-algorithm")) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 108739f..32feac5 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -126,14 +126,14 @@ struct stmmac_axi { struct stmmac_rxq_cfg { u8 mode_to_use; - u8 chan; + u32 chan; u8 pkt_route; bool use_prio; u32 prio; }; struct stmmac_txq_cfg { - u8 weight; + u32 weight; u8 mode_to_use; /* Credit Base Shaper parameters */ u32 send_slope; @@ -168,8 +168,8 @@ struct plat_stmmacenet_data { int unicast_filter_entries; int tx_fifo_size; int rx_fifo_size; - u8 rx_queues_to_use; - u8 tx_queues_to_use; + u32 rx_queues_to_use; + u32 tx_queues_to_use; u8 rx_sched_algorithm; u8 tx_sched_algorithm; struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];