From patchwork Mon Jun 17 18:59:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1117393 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="CTQureyn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SLBJ4Q0tz9sNl for ; Tue, 18 Jun 2019 05:00:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726776AbfFQTAA (ORCPT ); Mon, 17 Jun 2019 15:00:00 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:25677 "EHLO esa5.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725497AbfFQS77 (ORCPT ); Mon, 17 Jun 2019 14:59:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1560797999; x=1592333999; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GED2GA9QcE13vUl5xR4mTzXTMt8Lm/cPPiiomsp+YVU=; b=CTQureynTTh6tI+Te55MGbsieRaBn+Pz3IJKzaVSXDaUPdz7d9rOGbXP 7Fxg78oxBBUDnV3NhiKrWnzqcYBgXglALhjWYaPeCAXvfTcQ7p8xfu0cS 9n7kSo0Zym/SIwjaclFs7GBlKwicl+0B5vhgZM7vxVETvFQk88WgBV376 7FTGkI+t+u+xfHOtQNj2Nl0LfPDMf73nei8syufrUGwwt/TKDyphdspfW svaIYJYUc9nk2OASZRPXtg8HhbtZ7UK98o6iE4s9ned+CipNlTYZgiMBD UW727ykgoCdSchceDV92CZcsKwi8QYRA+KY11JEBKtR19vc/xLqK6Lj21 A==; X-IronPort-AV: E=Sophos;i="5.63,386,1557158400"; d="scan'208";a="112032235" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 18 Jun 2019 02:59:59 +0800 IronPort-SDR: 6Hh3HAIXCsjyBHZroPvc+BoVZgprG7Nt32ljyu0uEZlXS2MQt/9UIYk6zGMZK+ngj3TQMr3bhk KbOuU3mt2EsNf2lvXuesjgxHJOstN/+giDL9jgJKpilQRsccSGIK8L/ZN6Qvk2agntWt1uFhB5 PwtiM611zfjAhQEJLq/0unPxJIQID73Id+qBDxyI7/Bj06FxzRMaBwp/3Q0RbfgaviwpWIkuDE xwL3140C6K4JI0Jh3W49Ule+HWBpxBo4CHNxgIMfv6K3N8inFbaPnasuiXQLO1CDh0K4K2DrN6 7sec2e5fY6pWliWTDTlqthmL Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 17 Jun 2019 11:59:29 -0700 IronPort-SDR: IwDlxCoeIEV9birPttBGRyAxGoo4PO9XDI2b6rv6So20SSp7gpuKqDYkVfcj/YgAbcIDEX5xrT zYriFHD9jzhIykf8rB1NYxOkxuLmX63honLpoHi1q20Jm3flrEUNsIYZSBUgfLLHB64iyw6FyK 0waelF1QmvcpSgo00XeILtQHPXonfea34Z56vH/bd/QfZV64qpzowK9j4qXnHfDfiNg845p9sN fwrwNn3yuuI6f/dOANfN3s8Ud38GRQkHl1TlzmvYgjYWhQjjCutzZiUQghSMX/hNiQC2NfVp3N wk4= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Jun 2019 11:59:57 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Sudeep Holla , Rob Herring , Albert Ou , Anup Patel , Atish Patra , Catalin Marinas , "David S. Miller" , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jonathan Cameron , Linus Walleij , linux-riscv@lists.infradead.org, Mark Rutland , Mauro Carvalho Chehab , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Richard Fontana , Rob Herring , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH v7 1/7] Documentation: DT: arm: add support for sockets defining package boundaries Date: Mon, 17 Jun 2019 11:59:14 -0700 Message-Id: <20190617185920.29581-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190617185920.29581-1-atish.patra@wdc.com> References: <20190617185920.29581-1-atish.patra@wdc.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sudeep Holla The current ARM DT topology description provides the operating system with a topological view of the system that is based on leaf nodes representing either cores or threads (in an SMT system) and a hierarchical set of cluster nodes that creates a hierarchical topology view of how those cores and threads are grouped. However this hierarchical representation of clusters does not allow to describe what topology level actually represents the physical package or the socket boundary, which is a key piece of information to be used by an operating system to optimize resource allocation and scheduling. Lets add a new "socket" node type in the cpu-map node to describe the same. Signed-off-by: Sudeep Holla Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/topology.txt | 52 ++++++++++++++----- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt index b0d80c0fb265..3b8febb46dad 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/arm/topology.txt @@ -9,6 +9,7 @@ ARM topology binding description In an ARM system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: +- socket - cluster - core - thread @@ -63,21 +64,23 @@ nodes are listed. The cpu-map node's child nodes can be: - - one or more cluster nodes + - one or more cluster nodes or + - one or more socket nodes in a multi-socket system Any other configuration is considered invalid. -The cpu-map node can only contain three types of child nodes: +The cpu-map node can only contain 4 types of child nodes: +- socket node - cluster node - core node - thread node whose bindings are described in paragraph 3. -The nodes describing the CPU topology (cluster/core/thread) can only -be defined within the cpu-map node and every core/thread in the system -must be defined within the topology. Any other configuration is +The nodes describing the CPU topology (socket/cluster/core/thread) can +only be defined within the cpu-map node and every core/thread in the +system must be defined within the topology. Any other configuration is invalid and therefore must be ignored. =========================================== @@ -85,26 +88,44 @@ invalid and therefore must be ignored. =========================================== cpu-map child nodes must follow a naming convention where the node name -must be "clusterN", "coreN", "threadN" depending on the node type (ie -cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which -are siblings within a single common parent node must be given a unique and +must be "socketN", "clusterN", "coreN", "threadN" depending on the node type +(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes +which are siblings within a single common parent node must be given a unique and sequential N value, starting from 0). cpu-map child nodes which do not share a common parent node can have the same name (ie same number N as other cpu-map child nodes at different device tree levels) since name uniqueness will be guaranteed by the device tree hierarchy. =========================================== -3 - cluster/core/thread node bindings +3 - socket/cluster/core/thread node bindings =========================================== -Bindings for cluster/cpu/thread nodes are defined as follows: +Bindings for socket/cluster/cpu/thread nodes are defined as follows: + +- socket node + + Description: must be declared within a cpu-map node, one node + per physical socket in the system. A system can + contain single or multiple physical socket. + The association of sockets and NUMA nodes is beyond + the scope of this bindings, please refer [2] for + NUMA bindings. + + This node is optional for a single socket system. + + The socket node name must be "socketN" as described in 2.1 above. + A socket node can not be a leaf node. + + A socket node's child nodes must be one or more cluster nodes. + + Any other configuration is considered invalid. - cluster node Description: must be declared within a cpu-map node, one node per cluster. A system can contain several layers of - clustering and cluster nodes can be contained in parent - cluster nodes. + clustering within a single physical socket and cluster + nodes can be contained in parent cluster nodes. The cluster node name must be "clusterN" as described in 2.1 above. A cluster node can not be a leaf node. @@ -164,13 +185,15 @@ Bindings for cluster/cpu/thread nodes are defined as follows: 4 - Example dts =========================================== -Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters): +Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single +physical socket): cpus { #size-cells = <0>; #address-cells = <2>; cpu-map { + socket0 { cluster0 { cluster0 { core0 { @@ -253,6 +276,7 @@ cpus { }; }; }; + }; CPU0: cpu@0 { device_type = "cpu"; @@ -473,3 +497,5 @@ cpus { =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml +[2] Devicetree NUMA binding description + Documentation/devicetree/bindings/numa.txt From patchwork Mon Jun 17 18:59:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1117392 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="DNaZRgL4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SLBH6Fnlz9sNT for ; Tue, 18 Jun 2019 05:00:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727850AbfFQTAD (ORCPT ); Mon, 17 Jun 2019 15:00:03 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:25677 "EHLO esa5.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725497AbfFQTAD (ORCPT ); Mon, 17 Jun 2019 15:00:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1560798002; x=1592334002; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UlrSFoZF245E1zwQ107bOTMAJdrUzCCLZvF7b0tZ2tg=; b=DNaZRgL4zdHRpJ0/KqEpt2hJbr5FbUlcM7ZvQbUr4X+NZYnqKIGNdliD aHBb4os7GYuoQLc4N2LJ9NBeGtbxqra4vZkWPuo9v78nRfX7RGBdNWMvJ L1iAxTOlLXBnKgRTeztiUA29EFEZyGxgktkMi/4H+V/p0oKdzldaZMAj0 i468KVcIDqoZnxVdSzDPlU7B4mms0wZy1YTqteBajGY8sSsNlvcFz2nrK k+RMsPZmV1yfIMqam4UGGzuCEFCqvJSUdW+6wCnQ3w8H6VP3PIaAQ0Zd+ dal9pxfVSQbd8mb4Wet0SJ4njgeYqAqkaoNfewUc1ifr5R48j5/RDeplm g==; X-IronPort-AV: E=Sophos;i="5.63,386,1557158400"; d="scan'208";a="112032238" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 18 Jun 2019 03:00:02 +0800 IronPort-SDR: 919iY3XecezQUxKfAYKV5ygTKcGN/SIjwLoZuABqQvKSgX/GusjX0cdHeAYr1oLJtke14Xs+O4 DDR3K0IJG9e/XxDLKzVhjyL5sQ7nlW9s/kGJC1lEx3p5b17wWMblVm+K1Y1wY/G29aV2gbYSgz cTGLNLaWJYXKdMMCUpUohtDGjrkTwV3mO4rjeFBLuJ71UxII/vW0l6b/6UFeitZfJ75b/aHb/C 3HRiiOZss5bCJbLH/OQ/LM+vhOvh6ZtdaTIayo1rhCa8PxqXqtkm9x5F+UwPazxmHlJ9BHFKaf NAKIxeSH+uDYnRqMc5mySgVx Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 17 Jun 2019 11:59:32 -0700 IronPort-SDR: 2JCAxVtBfWf1/Ip4AceK27iqaxL+NW3HV0REmdIwrZdIKaJV7MLPgJoQvMo+OZnCZNRlIoSgLp 9VknH29VOR/yaYD3b2reDdPQ9aD/0K9uA82ve3SpcQLpUmNwIWBUoK8fxouDSu7VWjdcXiodPw KFxPoPu0UI+H+NJ1ZZ7D5H7FYqphh5l1w0zcU/wf6d6M4OQHwDpyezfHdqpboj1dhKEBfDmYQX dQXMdzFtB0CfoUcdKGZqE1lOmHzKaZKG8C8Jhrm7vi4dVBxaFidyWsLY52H5w2k3RtkFpPy6yT aGQ= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Jun 2019 12:00:00 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Sudeep Holla , Rob Herring , Albert Ou , Anup Patel , Catalin Marinas , "David S. Miller" , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jonathan Cameron , Linus Walleij , linux-riscv@lists.infradead.org, Mark Rutland , Mauro Carvalho Chehab , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Richard Fontana , Rob Herring , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH v7 2/7] dt-binding: cpu-topology: Move cpu-map to a common binding. Date: Mon, 17 Jun 2019 11:59:15 -0700 Message-Id: <20190617185920.29581-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190617185920.29581-1-atish.patra@wdc.com> References: <20190617185920.29581-1-atish.patra@wdc.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra Reviewed-by: Sudeep Holla Reviewed-by: Rob Herring --- .../topology.txt => cpu/cpu-topology.txt} | 84 +++++++++++++++---- 1 file changed, 68 insertions(+), 16 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt similarity index 86% rename from Documentation/devicetree/bindings/arm/topology.txt rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt index 3b8febb46dad..99918189403c 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt @@ -1,12 +1,12 @@ =========================================== -ARM topology binding description +CPU topology binding description =========================================== =========================================== 1 - Introduction =========================================== -In an ARM system, the hierarchy of CPUs is defined through three entities that +In a SMP system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: - socket @@ -14,9 +14,6 @@ are used to describe the layout of physical CPUs in the system: - core - thread -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - The bottom hierarchy level sits at core or thread level depending on whether symmetric multi-threading (SMT) is supported or not. @@ -25,33 +22,31 @@ threads existing in the system and map to the hierarchy level "thread" above. In systems where SMT is not supported "cpu" nodes represent all cores present in the system and map to the hierarchy level "core" above. -ARM topology bindings allow one to associate cpu nodes with hierarchical groups +CPU topology bindings allow one to associate cpu nodes with hierarchical groups corresponding to the system hierarchy; syntactically they are defined as device tree nodes. -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: +Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be +used for any other architecture as well. -https://www.devicetree.org/specifications/ +The cpu nodes, as per bindings defined in [4], represent the devices that +correspond to physical CPUs and are to be mapped to the hierarchy levels. -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. +with bindings standardized in [4] is therefore considered invalid. =========================================== 2 - cpu-map node =========================================== -The ARM CPU topology is defined within the cpu-map node, which is a direct +The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct child of the cpus node and provides a container where the actual topology nodes are listed. - cpu-map node - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology + Usage: Optional - On SMP systems provide CPUs topology to the OS. + Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. @@ -494,8 +489,65 @@ cpus { }; }; +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) + +{ + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + ... + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + socket0 { + cluster0 { + core0 { + cpu = <&CPU1>; + }; + core1 { + cpu = <&CPU2>; + }; + core2 { + cpu0 = <&CPU2>; + }; + core3 { + cpu0 = <&CPU3>; + }; + }; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x1>; + } + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x2>; + } + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x3>; + } + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x4>; + } + } +}; =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml [2] Devicetree NUMA binding description Documentation/devicetree/bindings/numa.txt +[3] RISC-V Linux kernel documentation + Documentation/devicetree/bindings/riscv/cpus.txt +[4] https://www.devicetree.org/specifications/