From patchwork Mon Jun 17 18:42:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1117331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-503117-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="L0HGqcFg"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mG3Fe15q"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45SKpJ02lKz9sNm for ; Tue, 18 Jun 2019 04:42:45 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=gkzMwlBnxHrE5WPk50VI4AFfo/HE3UNu0CxDvB+yowgWfk Gvh/vX47HPkvCinyorh+Nz8RwRsII1HmVJkgHiHhpQcvFNe6Uic6dpvENIfDfGXT Ufaojr5jGDF6TP1H8ZuiYyNJz7ICjj3dBmCyErbYqD6cggqwAj8MOU4m3Axrc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=5RwLqTUPWWaOITvlI5BNxT6eN3g=; b=L0HGqcFg5ByT+/8euvOu 0Xuu3RQhCd23zp3ITeV90LLGp0rj19hUk7fsCQZZB+1ZShdR0vrnaLkDNKKAgpSy wLXiOee6H22amD6lsyL4ojugobKa7jE9UCHEwPFh5TucYYy/ep4Z3EkJz7a1OY7h uytHPMPgr/NQCGh5JhijU5Y= Received: (qmail 93487 invoked by alias); 17 Jun 2019 18:42:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 93478 invoked by uid 89); 17 Jun 2019 18:42:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=por X-HELO: mail-io1-f48.google.com Received: from mail-io1-f48.google.com (HELO mail-io1-f48.google.com) (209.85.166.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Jun 2019 18:42:35 +0000 Received: by mail-io1-f48.google.com with SMTP id n5so23498700ioc.7 for ; Mon, 17 Jun 2019 11:42:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=6QZua1bBkOla71UDd7CDGjPsHJBtw09cHj0Tyrnff7I=; b=mG3Fe15q4CYS4SlDs/3oGX6oRuYqKiDi/SWV4ynKIsU/CWYtAEzcv97NrEe5bQ4AhG 2gRBh5JrSaOVvQq08lLuKONMJWmgIQRyUBGicT+mWWzDAIwecEWScOeqfQ/dMOpVH5te HPQs6AvX+OaqMqw6+1/2tNTscU6N8ZbtogbPCCh1SIbgacT4cAinE/NjOWH2IEPOYXkJ kvyAUAJL8ffM9uDVnnulwC9yUmgptzGW/K1mv8LFBJ0pTTcPCsH1BOo7M4w8a0y01Gvp UDobpp16dhHX3W6YfMDmuk6RbJMoDF0kp62QQqrCbBf/DL8F4DK/J2IeB77H3KxFSsO0 wD9w== MIME-Version: 1.0 From: Uros Bizjak Date: Mon, 17 Jun 2019 20:42:22 +0200 Message-ID: Subject: [PATCH, i386]: Fix PR 62055, recognize fnabs (FP negative absolute value) To: "gcc-patches@gcc.gnu.org" 2019-06-17 Uroš Bizjak PR target/62055 * config/i386/i386.md (*nabstf2_1): New insn pattern. (*nabs2_1): Ditto. (nabs sse-reg splitter): New splitter. * config/i386/sse.md (*nabs2): New insn_and_split pattern. testsuite/ChangeLog: 2019-06-17 Uroš Bizjak PR target/62055 * gcc.target/i386/fnabs.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 272386) +++ config/i386/i386.md (working copy) @@ -9452,6 +9452,16 @@ "#" [(set_attr "isa" "noavx,noavx,avx,avx")]) +(define_insn "*nabstf2_1" + [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv") + (neg:TF + (abs:TF + (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m")))) + (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv"))] + "TARGET_SSE" + "#" + [(set_attr "isa" "noavx,noavx,avx,avx")]) + (define_expand "2" [(set (match_operand:X87MODEF 0 "register_operand") (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] @@ -9553,6 +9563,48 @@ [(const_int 0)] "ix86_split_fp_absneg_operator (, mode, operands); DONE;") +(define_insn "*nabs2_1" + [(set (match_operand:MODEF 0 "register_operand" "=x,x,Yv") + (neg:MODEF + (abs:MODEF + (match_operand:MODEF 1 "register_operand" "0,x,Yv")))) + (use (match_operand: 2 "vector_operand" "xBm,0,Yvm"))] + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" + "#" + [(set_attr "isa" "noavx,noavx,avx")]) + +(define_split + [(set (match_operand:SSEMODEF 0 "sse_reg_operand") + (neg:SSEMODEF + (abs:SSEMODEF + (match_operand:SSEMODEF 1 "vector_operand")))) + (use (match_operand: 2 "vector_operand"))] + "((SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || (TARGET_SSE && (mode == TFmode))) + && reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + machine_mode mode = mode; + machine_mode vmode = mode; + + operands[0] = lowpart_subreg (vmode, operands[0], mode); + operands[1] = lowpart_subreg (vmode, operands[1], mode); + + if (TARGET_AVX) + { + if (MEM_P (operands[1])) + std::swap (operands[1], operands[2]); + } + else + { + if (operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); + } + + operands[3] + = gen_rtx_fmt_ee (IOR, vmode, operands[1], operands[2]); +}) + ;; Conditionalize these after reload. If they match before reload, we ;; lose the clobber and ability to use integer instructions. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 272386) +++ config/i386/sse.md (working copy) @@ -1748,6 +1748,33 @@ } [(set_attr "isa" "noavx,noavx,avx,avx")]) +(define_insn_and_split "*nabs2" + [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") + (neg:VF + (abs:VF + (match_operand:VF 1 "vector_operand" "0,xBm,v,m")))) + (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + if (TARGET_AVX) + { + if (MEM_P (operands[1])) + std::swap (operands[1], operands[2]); + } + else + { + if (operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); + } + + operands[3] + = gen_rtx_fmt_ee (IOR, mode, operands[1], operands[2]); +} + [(set_attr "isa" "noavx,noavx,avx,avx")]) + (define_expand "3" [(set (match_operand:VF 0 "register_operand") (plusminus:VF Index: testsuite/gcc.target/i386/fnabs.c =================================================================== --- testsuite/gcc.target/i386/fnabs.c (nonexistent) +++ testsuite/gcc.target/i386/fnabs.c (working copy) @@ -0,0 +1,21 @@ +/* PR target/62055 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mfpmath=sse" } */ + +float testf (float a) +{ + return -__builtin_fabsf (a); +} + +double test (double a) +{ + return -__builtin_fabs (a); +} + +__float128 testq (__float128 a) +{ + return -__builtin_fabsq (a); +} + +/* { dg-final { scan-assembler-times "\tv?orp\[sd\]\[ \t\]" 2 } } */ +/* { dg-final { scan-assembler-times "\tv?por\[ \t\]" 1 } } */