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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6826 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-16_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906160067 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is version 2 of patch to add support for SGMII interface) and 2.5Gbps MAC in Cadence ethernet controller driver. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 76 +++++++++-- drivers/net/ethernet/cadence/macb_main.c | 157 ++++++++++++++++++++--- 2 files changed, 202 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 35ed13236c8b..85c7e4cb1057 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -80,6 +80,7 @@ #define MACB_RBQPH 0x04D4 /* GEM register offsets. */ +#define GEM_NCR 0x0000 /* Network Control */ #define GEM_NCFGR 0x0004 /* Network Config */ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ @@ -159,6 +160,9 @@ #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ +#define GEM_PCS_CTRL 0x0200 /* PCS Control */ +#define GEM_PCS_STATUS 0x0204 /* PCS Status */ +#define GEM_PCS_AN_LP_BASE 0x0214 /* PCS AN LP BASE*/ #define GEM_DCFG1 0x0280 /* Design Config 1 */ #define GEM_DCFG2 0x0284 /* Design Config 2 */ #define GEM_DCFG3 0x0288 /* Design Config 3 */ @@ -274,6 +278,10 @@ #define MACB_IRXFCS_OFFSET 19 #define MACB_IRXFCS_SIZE 1 +/* GEM specific NCR bitfields. */ +#define GEM_TWO_PT_FIVE_GIG_OFFSET 29 +#define GEM_TWO_PT_FIVE_GIG_SIZE 1 + /* GEM specific NCFGR bitfields. */ #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ #define GEM_GBE_SIZE 1 @@ -326,6 +334,9 @@ #define MACB_MDIO_SIZE 1 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ #define MACB_IDLE_SIZE 1 +#define MACB_DUPLEX_OFFSET 3 +#define MACB_DUPLEX_SIZE 1 + /* Bitfields in TSR */ #define MACB_UBR_OFFSET 0 /* Used bit read */ @@ -459,11 +470,37 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfields in PCS_CONTROL. */ +#define GEM_PCS_CTRL_RST_OFFSET 15 +#define GEM_PCS_CTRL_RST_SIZE 1 +#define GEM_PCS_CTRL_EN_AN_OFFSET 12 +#define GEM_PCS_CTRL_EN_AN_SIZE 1 +#define GEM_PCS_CTRL_RESTART_AN_OFFSET 9 +#define GEM_PCS_CTRL_RESTART_AN_SIZE 1 + +/* Bitfields in PCS_STATUS. */ +#define GEM_PCS_STATUS_AN_DONE_OFFSET 5 +#define GEM_PCS_STATUS_AN_DONE_SIZE 1 +#define GEM_PCS_STATUS_AN_SUPPORT_OFFSET 3 +#define GEM_PCS_STATUS_AN_SUPPORT_SIZE 1 +#define GEM_PCS_STATUS_LINK_OFFSET 2 +#define GEM_PCS_STATUS_LINK_SIZE 1 + +/* Bitfield in PCS_AN_LP_BASE */ +#define GEM_PCS_AN_LP_BASE_LINK_OFFSET 15 +#define GEM_PCS_AN_LP_BASE_LINK_SIZE 1 +#define GEM_PCS_AN_LP_BASE_DUPLEX_OFFSET 12 +#define GEM_PCS_AN_LP_BASE_DUPLEX_SIZE 1 +#define GEM_PCS_AN_LP_BASE_SPEED_OFFSET 10 +#define GEM_PCS_AN_LP_BASE_SPEED_SIZE 2 + /* Bitfields in DCFG1. */ #define GEM_IRQCOR_OFFSET 23 #define GEM_IRQCOR_SIZE 1 #define GEM_DBWDEF_OFFSET 25 #define GEM_DBWDEF_SIZE 3 +#define GEM_NO_PCS_OFFSET 0 +#define GEM_NO_PCS_SIZE 1 /* Bitfields in DCFG2. */ #define GEM_RX_PKT_BUFF_OFFSET 20 @@ -636,19 +673,32 @@ #define MACB_MAN_CODE 2 /* Capability mask bits */ -#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 -#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 -#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 -#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 -#define MACB_CAPS_USRIO_DISABLED 0x00000010 -#define MACB_CAPS_JUMBO 0x00000020 -#define MACB_CAPS_GEM_HAS_PTP 0x00000040 -#define MACB_CAPS_BD_RD_PREFETCH 0x00000080 -#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 -#define MACB_CAPS_FIFO_MODE 0x10000000 -#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 -#define MACB_CAPS_SG_DISABLED 0x40000000 -#define MACB_CAPS_MACB_IS_GEM 0x80000000 +#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0) +#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1) +#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2) +#define MACB_CAPS_NO_GIGABIT_HALF BIT(3) +#define MACB_CAPS_USRIO_DISABLED BIT(4) +#define MACB_CAPS_JUMBO BIT(5) +#define MACB_CAPS_GEM_HAS_PTP BIT(6) +#define MACB_CAPS_BD_RD_PREFETCH BIT(7) +#define MACB_CAPS_NEEDS_RSTONUBR BIT(8) +#define MACB_CAPS_FIFO_MODE BIT(28) +#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29) +#define MACB_CAPS_SG_DISABLED BIT(30) +#define MACB_CAPS_MACB_IS_GEM BIT(31) +#define MACB_CAPS_PCS BIT(24) +#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25) + +#define MACB_GEM7010_IDNUM 0x009 +#define MACB_GEM7014_IDNUM 0x107 +#define MACB_GEM7014A_IDNUM 0x207 +#define MACB_GEM7016_IDNUM 0x10a +#define MACB_GEM7017_IDNUM 0x00a +#define MACB_GEM7017A_IDNUM 0x20a +#define MACB_GEM7020_IDNUM 0x003 +#define MACB_GEM7021_IDNUM 0x00c +#define MACB_GEM7021A_IDNUM 0x20c +#define MACB_GEM7022_IDNUM 0x00b /* LSO settings */ #define MACB_LSO_UFO_ENABLE 0x01 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 52d5e5efe2ad..5b3e7d9f4384 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -394,6 +394,7 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) { long ferr, rate, rate_rounded; + struct macb *bp = netdev_priv(dev); if (!clk) return; @@ -408,6 +409,12 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) case SPEED_1000: rate = 125000000; break; + case SPEED_2500: + if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) + rate = 312500000; + else + rate = 125000000; + break; default: return; } @@ -438,15 +445,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config, __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) + phylink_set(mask, 2500baseT_Full); + /* fallthrough */ case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII: if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); - if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) { - phylink_set(mask, 1000baseT_Half); + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) phylink_set(mask, 1000baseT_Half); - } } /* fallthrough */ case PHY_INTERFACE_MODE_MII: @@ -456,6 +464,16 @@ static void gem_phylink_validate(struct phylink_config *pl_config, phylink_set(mask, 100baseT_Half); phylink_set(mask, 100baseT_Full); break; + + case PHY_INTERFACE_MODE_2500BASEX: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) + phylink_set(mask, 2500baseX_Full); + /* fallthrough */ + case PHY_INTERFACE_MODE_1000BASEX: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) + phylink_set(mask, 1000baseX_Full); + break; + default: break; } @@ -468,15 +486,54 @@ static void gem_phylink_validate(struct phylink_config *pl_config, static int gem_phylink_mac_link_state(struct phylink_config *pl_config, struct phylink_link_state *state) { + u32 status; struct net_device *netdev = to_net_dev(pl_config->dev); struct macb *bp = netdev_priv(netdev); - state->speed = bp->speed; - state->duplex = bp->duplex; - state->link = bp->link; + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { + status = gem_readl(bp, PCS_STATUS); + state->an_complete = GEM_BFEXT(PCS_STATUS_AN_DONE, status); + status = gem_readl(bp, PCS_AN_LP_BASE); + switch (GEM_BFEXT(PCS_AN_LP_BASE_SPEED, status)) { + case 0: + state->speed = 10; + break; + case 1: + state->speed = 100; + break; + case 2: + state->speed = 1000; + break; + default: + break; + } + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR)); + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR)); + } else if (bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + state->speed = SPEED_2500; + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR)); + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR)); + } else if (bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { + state->speed = SPEED_1000; + state->duplex = MACB_BFEXT(DUPLEX, macb_readl(bp, NSR)); + state->link = MACB_BFEXT(NSR_LINK, macb_readl(bp, NSR)); + } return 1; } +static void gem_mac_an_restart(struct phylink_config *pl_config) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_RESTART_AN)); + } +} + static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, const struct phylink_link_state *state) { @@ -494,17 +551,23 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); if (macb_is_gem(bp)) reg &= ~GEM_BIT(GBE); - if (state->duplex) reg |= MACB_BIT(FD); - if (state->speed == SPEED_100) - reg |= MACB_BIT(SPD); - if (state->speed == SPEED_1000 && - bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) - reg |= GEM_BIT(GBE); - macb_or_gem_writel(bp, NCFGR, reg); + if (state->speed == SPEED_2500) { + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) | + gem_readl(bp, NCR)); + } else if (state->speed == SPEED_1000) { + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + } else if (state->speed == SPEED_100) { + macb_writel(bp, NCFGR, MACB_BIT(SPD) | + macb_readl(bp, NCFGR)); + } + bp->speed = state->speed; bp->duplex = state->duplex; @@ -541,6 +604,7 @@ static void gem_mac_link_down(struct phylink_config *pl_config, static const struct phylink_mac_ops gem_phylink_ops = { .validate = gem_phylink_validate, .mac_link_state = gem_phylink_mac_link_state, + .mac_an_restart = gem_mac_an_restart, .mac_config = gem_mac_config, .mac_link_up = gem_mac_link_up, .mac_link_down = gem_mac_link_down, @@ -2245,7 +2309,9 @@ static void macb_init_hw(struct macb *bp) macb_set_hwaddr(bp); config = macb_mdc_clk_div(bp); - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ config |= MACB_BIT(PAE); /* PAuse Enable */ @@ -2270,6 +2336,17 @@ static void macb_init_hw(struct macb *bp) if (bp->caps & MACB_CAPS_JUMBO) bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + //Enable PCS AN + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_EN_AN)); + //Reset PCS block + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_RST)); + } + macb_configure_dma(bp); /* Initialize TX and RX buffers */ @@ -3361,6 +3438,22 @@ static void macb_configure_caps(struct macb *bp, dcfg = gem_readl(bp, DCFG1); if (GEM_BFEXT(IRQCOR, dcfg) == 0) bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; + if (GEM_BFEXT(NO_PCS, dcfg) == 0) + bp->caps |= MACB_CAPS_PCS; + switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) { + case MACB_GEM7016_IDNUM: + case MACB_GEM7017_IDNUM: + case MACB_GEM7017A_IDNUM: + case MACB_GEM7020_IDNUM: + case MACB_GEM7021_IDNUM: + case MACB_GEM7021A_IDNUM: + case MACB_GEM7022_IDNUM: + bp->caps |= MACB_CAPS_USRIO_DISABLED; + bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL; + break; + default: + break; + } dcfg = gem_readl(bp, DCFG2); if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) bp->caps |= MACB_CAPS_FIFO_MODE; @@ -3649,7 +3742,9 @@ static int macb_init(struct platform_device *pdev) /* Set MII management clock divider */ val = macb_mdc_clk_div(bp); val |= macb_dbw(bp); - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); macb_writel(bp, NCFGR, val); @@ -4232,11 +4327,37 @@ static int macb_probe(struct platform_device *pdev) } err = of_get_phy_mode(np); - if (err < 0) + if (err < 0) { /* not found in DT, MII by default */ bp->phy_interface = PHY_INTERFACE_MODE_MII; - else + } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) { + u32 interface_supported = 1; + + if (err == PHY_INTERFACE_MODE_SGMII || + err == PHY_INTERFACE_MODE_1000BASEX || + err == PHY_INTERFACE_MODE_2500BASEX) { + if (!(bp->caps & MACB_CAPS_PCS)) + interface_supported = 0; + } else if (err == PHY_INTERFACE_MODE_GMII || + err == PHY_INTERFACE_MODE_RGMII) { + if (!macb_is_gem(bp)) + interface_supported = 0; + } else if (err != PHY_INTERFACE_MODE_RMII && + err != PHY_INTERFACE_MODE_MII) { + /* Add new mode before this */ + interface_supported = 0; + } + + if (!interface_supported) { + netdev_err(dev, "Phy mode %s not supported", + phy_modes(err)); + goto err_out_free_netdev; + } + bp->phy_interface = err; + } else { + bp->phy_interface = err; + } /* IP specific init */ err = init(pdev); From patchwork Sun Jun 16 07:05:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1116499 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="DI8QVidC"; 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Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb_pci.c | 225 ++++++++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_pci.c b/drivers/net/ethernet/cadence/macb_pci.c index 248a8fc45069..1001e03191a1 100644 --- a/drivers/net/ethernet/cadence/macb_pci.c +++ b/drivers/net/ethernet/cadence/macb_pci.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include "macb.h" @@ -37,6 +38,224 @@ #define GEM_PCLK_RATE 50000000 #define GEM_HCLK_RATE 50000000 +#define TI_PHY_DP83867_ID 0x2000a231 +#define TI_PHY_DEVADDR 0x1f +#define PHY_REGCR 0x0D +#define PHY_ADDAR 0x0E + +#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ + +#define MACB_REGCR_OP_OFFSET 14 +#define MACB_REGCR_OP_SIZE 2 +#define MACB_REGCR_DEVADDR_OFFSET 0 +#define MACB_REGCR_DEVADDR_SIZE 5 + +#define MACB_REGCR_OP_ADDR 0 +#define MACB_REGCR_OP_DATA 1 + +static int macb_mdio_wait_for_idle(void __iomem *macb_base_addr) +{ + u32 val; + + return readx_poll_timeout(readl, macb_base_addr + MACB_NSR, val, + val & MACB_BIT(IDLE), 1, MACB_MDIO_TIMEOUT); +} + +static int macb_mdiobus_read(void __iomem *macb_base_addr, + u32 phy_id, + u32 regnum) +{ + u32 i; + int status; + + if (regnum < 32) { + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_READ) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, regnum) | + MACB_BF(CODE, MACB_MAN_CODE); + + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + } else { + u16 reg; + + reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_ADDR) | + MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_REGCR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, reg); + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_ADDAR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, regnum); + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + + reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_DATA) | + MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_REGCR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, reg); + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_READ) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_ADDAR) | + MACB_BF(CODE, MACB_MAN_CODE); + + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + } + + return readl(macb_base_addr + MACB_MAN); +} + +static int macb_mdiobus_write(void __iomem *macb_base_addr, u32 phy_id, + u32 regnum, u16 value) +{ + u32 i; + int status; + + if (regnum < 32) { + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, regnum) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, value); + + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + } else { + u16 reg; + + reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_ADDR) | + MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_REGCR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, reg); + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_ADDAR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, regnum); + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + + reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_DATA) | + MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_REGCR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, reg); + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + + i = MACB_BF(SOF, MACB_MAN_SOF) | + MACB_BF(RW, MACB_MAN_WRITE) | + MACB_BF(PHYA, phy_id) | + MACB_BF(REGA, PHY_ADDAR) | + MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(DATA, value); + + writel(i, macb_base_addr + MACB_MAN); + status = macb_mdio_wait_for_idle(macb_base_addr); + if (status < 0) + return status; + } + + return 0; +} + +static int macb_scan_mdio(void __iomem *macb_base_addr) +{ + int i; + int phy_reg; + int phy_id; + + for (i = 0; i < PHY_MAX_ADDR; i++) { + phy_reg = macb_mdiobus_read(macb_base_addr, i, MII_PHYSID1); + if (phy_reg < 0) + continue; + + phy_id = (phy_reg & 0xffff) << 16; + phy_reg = macb_mdiobus_read(macb_base_addr, i, MII_PHYSID2); + if (phy_reg < 0) + continue; + + phy_id |= (phy_reg & 0xffff); + if ((phy_id & 0x1fffffff) != 0x1fffffff && + phy_id == TI_PHY_DP83867_ID) + return i; + } + + return -1; +} + +static void macb_setup_phy(void __iomem *macb_base_addr) +{ + int phy_id; + + // Enable MDIO + writel(readl(macb_base_addr + MACB_NCR) | MACB_BIT(MPE), + macb_base_addr + MACB_NCR); + + phy_id = macb_scan_mdio(macb_base_addr); + if (phy_id >= 0) { + if (macb_mdiobus_write(macb_base_addr, phy_id, 0xd3, 0x4000)) + return; + if (macb_mdiobus_write(macb_base_addr, phy_id, 0x14, 0x29c7)) + return; + if (macb_mdiobus_write(macb_base_addr, phy_id, 0x32, 0x0000)) + return; + if (macb_mdiobus_write(macb_base_addr, phy_id, 0x10, 0x0800)) + return; + if (macb_mdiobus_write(macb_base_addr, phy_id, 0x31, 0x1170)) + return; + } +} + static int macb_probe(struct pci_dev *pdev, const struct pci_device_id *id) { int err; @@ -44,6 +263,7 @@ static int macb_probe(struct pci_dev *pdev, const struct pci_device_id *id) struct platform_device_info plat_info; struct macb_platform_data plat_data; struct resource res[2]; + void __iomem *addr; /* enable pci device */ err = pcim_enable_device(pdev); @@ -66,6 +286,11 @@ static int macb_probe(struct pci_dev *pdev, const struct pci_device_id *id) dev_info(&pdev->dev, "EMAC physical base addr: %pa\n", &res[0].start); + addr = ioremap(res[0].start, resource_size(&res[0])); + if (addr) { + macb_setup_phy(addr); + iounmap(addr); + } /* set up macb platform data */ memset(&plat_data, 0, sizeof(plat_data)); From patchwork Sun Jun 16 07:05:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1116500 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="nWKU4kqS"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="TbukwIvh"; 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Ip=[199.43.4.28]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR07MB6820 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-16_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=810 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906160067 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch modify MDIO read/write functions to support communication with C45 PHY. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 15 ++++-- drivers/net/ethernet/cadence/macb_main.c | 61 +++++++++++++++++++----- drivers/net/ethernet/cadence/macb_pci.c | 60 +++++++++++------------ 3 files changed, 91 insertions(+), 45 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 85c7e4cb1057..75f093bc52fe 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -667,10 +667,17 @@ #define GEM_CLK_DIV96 5 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_C22_SOF 1 +#define MACB_MAN_C22_WRITE 1 +#define MACB_MAN_C22_READ 2 +#define MACB_MAN_C22_CODE 2 + +#define MACB_MAN_C45_SOF 0 +#define MACB_MAN_C45_ADDR 0 +#define MACB_MAN_C45_WRITE 1 +#define MACB_MAN_C45_POST_READ_INCR 2 +#define MACB_MAN_C45_READ 3 +#define MACB_MAN_C45_CODE 2 /* Capability mask bits */ #define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 5b3e7d9f4384..57ffc4e9d2b9 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -334,11 +334,30 @@ static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) if (status < 0) goto mdio_read_exit; - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) - | MACB_BF(RW, MACB_MAN_READ) - | MACB_BF(PHYA, mii_id) - | MACB_BF(REGA, regnum) - | MACB_BF(CODE, MACB_MAN_CODE))); + if (regnum & MII_ADDR_C45) { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_ADDR) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(DATA, regnum & 0xFFFF) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + + status = macb_mdio_wait_for_idle(bp); + if (status < 0) + goto mdio_read_exit; + + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_READ) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + } else { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) + | MACB_BF(RW, MACB_MAN_C22_READ) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, regnum) + | MACB_BF(CODE, MACB_MAN_C22_CODE))); + } status = macb_mdio_wait_for_idle(bp); if (status < 0) @@ -367,12 +386,32 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, if (status < 0) goto mdio_write_exit; - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) - | MACB_BF(RW, MACB_MAN_WRITE) - | MACB_BF(PHYA, mii_id) - | MACB_BF(REGA, regnum) - | MACB_BF(CODE, MACB_MAN_CODE) - | MACB_BF(DATA, value))); + if (regnum & MII_ADDR_C45) { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_ADDR) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(DATA, regnum & 0xFFFF) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + + status = macb_mdio_wait_for_idle(bp); + if (status < 0) + goto mdio_write_exit; + + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_WRITE) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(CODE, MACB_MAN_C45_CODE) + | MACB_BF(DATA, value))); + } else { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) + | MACB_BF(RW, MACB_MAN_C22_WRITE) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, regnum) + | MACB_BF(CODE, MACB_MAN_C22_CODE) + | MACB_BF(DATA, value))); + } status = macb_mdio_wait_for_idle(bp); if (status < 0) diff --git a/drivers/net/ethernet/cadence/macb_pci.c b/drivers/net/ethernet/cadence/macb_pci.c index 1001e03191a1..23ca4557f45c 100644 --- a/drivers/net/ethernet/cadence/macb_pci.c +++ b/drivers/net/ethernet/cadence/macb_pci.c @@ -69,11 +69,11 @@ static int macb_mdiobus_read(void __iomem *macb_base_addr, int status; if (regnum < 32) { - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_READ) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_READ) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, regnum) | - MACB_BF(CODE, MACB_MAN_CODE); + MACB_BF(CODE, MACB_MAN_C22_CODE); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); @@ -84,22 +84,22 @@ static int macb_mdiobus_read(void __iomem *macb_base_addr, reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_ADDR) | MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_REGCR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, reg); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); if (status < 0) return status; - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_ADDAR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, regnum); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); @@ -108,22 +108,22 @@ static int macb_mdiobus_read(void __iomem *macb_base_addr, reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_DATA) | MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_REGCR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, reg); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); if (status < 0) return status; - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_READ) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_READ) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_ADDAR) | - MACB_BF(CODE, MACB_MAN_CODE); + MACB_BF(CODE, MACB_MAN_C22_CODE); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); @@ -141,11 +141,11 @@ static int macb_mdiobus_write(void __iomem *macb_base_addr, u32 phy_id, int status; if (regnum < 32) { - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, regnum) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, value); writel(i, macb_base_addr + MACB_MAN); @@ -157,22 +157,22 @@ static int macb_mdiobus_write(void __iomem *macb_base_addr, u32 phy_id, reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_ADDR) | MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_REGCR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, reg); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); if (status < 0) return status; - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_ADDAR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, regnum); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); @@ -181,22 +181,22 @@ static int macb_mdiobus_write(void __iomem *macb_base_addr, u32 phy_id, reg = MACB_BF(REGCR_OP, MACB_REGCR_OP_DATA) | MACB_BF(REGCR_DEVADDR, TI_PHY_DEVADDR); - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_REGCR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, reg); writel(i, macb_base_addr + MACB_MAN); status = macb_mdio_wait_for_idle(macb_base_addr); if (status < 0) return status; - i = MACB_BF(SOF, MACB_MAN_SOF) | - MACB_BF(RW, MACB_MAN_WRITE) | + i = MACB_BF(SOF, MACB_MAN_C22_SOF) | + MACB_BF(RW, MACB_MAN_C22_WRITE) | MACB_BF(PHYA, phy_id) | MACB_BF(REGA, PHY_ADDAR) | - MACB_BF(CODE, MACB_MAN_CODE) | + MACB_BF(CODE, MACB_MAN_C22_CODE) | MACB_BF(DATA, value); writel(i, macb_base_addr + MACB_MAN); From patchwork Sun Jun 16 07:05:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1116501 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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Ip=[158.140.1.28]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR07MB6830 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-16_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906160068 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch add support for high speed USXGMII PCS and 10G speed in Cadence ethernet controller driver. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 42 +++++ drivers/net/ethernet/cadence/macb_main.c | 215 +++++++++++++++++++---- 2 files changed, 224 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 75f093bc52fe..e00b9f647757 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -85,6 +85,7 @@ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ #define GEM_JML 0x0048 /* Jumbo Max Length */ +#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */ #define GEM_HRB 0x0080 /* Hash Bottom */ #define GEM_HRT 0x0084 /* Hash Top */ #define GEM_SA1B 0x0088 /* Specific1 Bottom */ @@ -172,6 +173,9 @@ #define GEM_DCFG7 0x0298 /* Design Config 7 */ #define GEM_DCFG8 0x029C /* Design Config 8 */ #define GEM_DCFG10 0x02A4 /* Design Config 10 */ +#define GEM_DCFG12 0x02AC /* Design Config 12 */ +#define GEM_USX_CONTROL 0x0A80 /* USXGMII control register */ +#define GEM_USX_STATUS 0x0A88 /* USXGMII status register */ #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ @@ -279,6 +283,8 @@ #define MACB_IRXFCS_SIZE 1 /* GEM specific NCR bitfields. */ +#define GEM_ENABLE_HS_MAC_OFFSET 31 +#define GEM_ENABLE_HS_MAC_SIZE 1 #define GEM_TWO_PT_FIVE_GIG_OFFSET 29 #define GEM_TWO_PT_FIVE_GIG_SIZE 1 @@ -470,6 +476,10 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfield in HS_MAC_CONFIG */ +#define GEM_HS_MAC_SPEED_OFFSET 0 +#define GEM_HS_MAC_SPEED_SIZE 3 + /* Bitfields in PCS_CONTROL. */ #define GEM_PCS_CTRL_RST_OFFSET 15 #define GEM_PCS_CTRL_RST_SIZE 1 @@ -535,6 +545,34 @@ #define GEM_RXBD_RDBUFF_OFFSET 8 #define GEM_RXBD_RDBUFF_SIZE 4 +/* Bitfields in DCFG12. */ +#define GEM_HIGH_SPEED_OFFSET 26 +#define GEM_HIGH_SPEED_SIZE 1 + +/* Bitfields in USX_CONTROL. */ +#define GEM_USX_CTRL_SPEED_OFFSET 14 +#define GEM_USX_CTRL_SPEED_SIZE 3 +#define GEM_SERDES_RATE_OFFSET 12 +#define GEM_SERDES_RATE_SIZE 2 +#define GEM_RX_SCR_BYPASS_OFFSET 9 +#define GEM_RX_SCR_BYPASS_SIZE 1 +#define GEM_TX_SCR_BYPASS_OFFSET 8 +#define GEM_TX_SCR_BYPASS_SIZE 1 +#define GEM_RX_SYNC_RESET_OFFSET 2 +#define GEM_RX_SYNC_RESET_SIZE 1 +#define GEM_TX_EN_OFFSET 1 +#define GEM_TX_EN_SIZE 1 +#define GEM_SIGNAL_OK_OFFSET 0 +#define GEM_SIGNAL_OK_SIZE 1 + +/* Bitfields in USX_STATUS. */ +#define GEM_USX_TX_FAULT_OFFSET 28 +#define GEM_USX_TX_FAULT_SIZE 1 +#define GEM_USX_RX_FAULT_OFFSET 27 +#define GEM_USX_RX_FAULT_SIZE 1 +#define GEM_USX_BLOCK_LOCK_OFFSET 0 +#define GEM_USX_BLOCK_LOCK_SIZE 1 + /* Bitfields in TISUBN */ #define GEM_SUBNSINCR_OFFSET 0 #define GEM_SUBNSINCR_SIZE 16 @@ -695,6 +733,7 @@ #define MACB_CAPS_MACB_IS_GEM BIT(31) #define MACB_CAPS_PCS BIT(24) #define MACB_CAPS_MACB_IS_GEM_GXL BIT(25) +#define MACB_CAPS_HIGH_SPEED BIT(26) #define MACB_GEM7010_IDNUM 0x009 #define MACB_GEM7014_IDNUM 0x107 @@ -774,6 +813,7 @@ }) #define MACB_READ_NSR(bp) macb_readl(bp, NSR) +#define GEM_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS) /* struct macb_dma_desc - Hardware DMA descriptor * @addr: DMA address of data buffer @@ -1287,6 +1327,8 @@ struct macb { struct macb_pm_data pm_data; struct phylink *pl; struct phylink_config pl_config; + u32 serdes_rate; + u32 fixed_speed; }; #ifdef CONFIG_MACB_USE_HWSTAMP diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 57ffc4e9d2b9..8739f815bcae 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -77,6 +77,20 @@ #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) #define MACB_WOL_ENABLED (0x1 << 1) +enum { + HS_MAC_SPEED_100M, + HS_MAC_SPEED_1000M, + HS_MAC_SPEED_2500M, + HS_MAC_SPEED_5000M, + HS_MAC_SPEED_10000M, + HS_MAC_SPEED_25000M, +}; + +enum { + MACB_SERDES_RATE_5_PT_15625Gbps, + MACB_SERDES_RATE_10_PT_3125Gbps, +}; + /* Graceful stop timeouts in us. We should allow up to * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) */ @@ -86,6 +100,8 @@ #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ +#define MACB_USX_BLOCK_LOCK_TIMEOUT 1000000 /* in usecs */ + /* DMA buffer descriptor might be different size * depends on hardware configuration: * @@ -438,24 +454,37 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) if (!clk) return; - switch (speed) { - case SPEED_10: - rate = 2500000; - break; - case SPEED_100: - rate = 25000000; - break; - case SPEED_1000: - rate = 125000000; - break; - case SPEED_2500: - if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) - rate = 312500000; - else + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + switch (bp->serdes_rate) { + case MACB_SERDES_RATE_5_PT_15625Gbps: + rate = 78125000; + break; + case MACB_SERDES_RATE_10_PT_3125Gbps: + rate = 156250000; + break; + default: + return; + } + } else { + switch (speed) { + case SPEED_10: + rate = 2500000; + break; + case SPEED_100: + rate = 25000000; + break; + case SPEED_1000: rate = 125000000; - break; - default: - return; + break; + case SPEED_2500: + if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) + rate = 312500000; + else + return; + break; + default: + return; + } } rate_rounded = clk_round_rate(clk, rate); @@ -484,6 +513,22 @@ static void gem_phylink_validate(struct phylink_config *pl_config, __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; switch (state->interface) { + case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GKR: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { + phylink_set(mask, 10000baseCR_Full); + phylink_set(mask, 10000baseER_Full); + phylink_set(mask, 10000baseKR_Full); + phylink_set(mask, 10000baseLR_Full); + phylink_set(mask, 10000baseLRM_Full); + phylink_set(mask, 10000baseSR_Full); + phylink_set(mask, 10000baseT_Full); + phylink_set(mask, 5000baseT_Full); + phylink_set(mask, 2500baseX_Full); + phylink_set(mask, 1000baseX_Full); + } + /* Fall-through */ case PHY_INTERFACE_MODE_SGMII: if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) phylink_set(mask, 2500baseT_Full); @@ -594,17 +639,55 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, reg |= MACB_BIT(FD); macb_or_gem_writel(bp, NCFGR, reg); - if (state->speed == SPEED_2500) { - gem_writel(bp, NCFGR, GEM_BIT(GBE) | - gem_readl(bp, NCFGR)); - gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) | - gem_readl(bp, NCR)); - } else if (state->speed == SPEED_1000) { - gem_writel(bp, NCFGR, GEM_BIT(GBE) | - gem_readl(bp, NCFGR)); - } else if (state->speed == SPEED_100) { - macb_writel(bp, NCFGR, MACB_BIT(SPD) | - macb_readl(bp, NCFGR)); + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + u32 speed; + + switch (state->speed) { + case SPEED_10000: + if (bp->serdes_rate == + MACB_SERDES_RATE_10_PT_3125Gbps) { + speed = HS_MAC_SPEED_10000M; + } else { + netdev_warn(netdev, + "10G not supported by HW"); + netdev_warn(netdev, "Setting speed to 1G"); + speed = HS_MAC_SPEED_1000M; + } + break; + case SPEED_5000: + speed = HS_MAC_SPEED_5000M; + break; + case SPEED_2500: + speed = HS_MAC_SPEED_2500M; + break; + case SPEED_1000: + speed = HS_MAC_SPEED_1000M; + break; + default: + case SPEED_100: + speed = HS_MAC_SPEED_100M; + break; + } + + gem_writel(bp, HS_MAC_CONFIG, + GEM_BFINS(HS_MAC_SPEED, speed, + gem_readl(bp, HS_MAC_CONFIG))); + gem_writel(bp, USX_CONTROL, + GEM_BFINS(USX_CTRL_SPEED, speed, + gem_readl(bp, USX_CONTROL))); + } else { + if (state->speed == SPEED_2500) { + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + gem_writel(bp, NCR, GEM_BIT(TWO_PT_FIVE_GIG) | + gem_readl(bp, NCR)); + } else if (state->speed == SPEED_1000) { + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + } else if (state->speed == SPEED_100) { + macb_writel(bp, NCFGR, MACB_BIT(SPD) | + macb_readl(bp, NCFGR)); + } } bp->speed = state->speed; @@ -649,6 +732,16 @@ static const struct phylink_mac_ops gem_phylink_ops = { .mac_link_down = gem_mac_link_down, }; +void gem_usx_fixed_state(struct net_device *dev, + struct phylink_link_state *state) +{ + struct macb *bp = netdev_priv(dev); + + state->speed = (bp->fixed_speed == SPEED_UNKNOWN) ? SPEED_1000 + : bp->fixed_speed; + state->duplex = 1; +} + /* based on au1000_eth. c*/ static int macb_mii_probe(struct net_device *dev) { @@ -670,6 +763,9 @@ static int macb_mii_probe(struct net_device *dev) return PTR_ERR(bp->pl); } + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) + phylink_fixed_state_cb(bp->pl, gem_usx_fixed_state); + ret = phylink_of_phy_connect(bp->pl, np, 0); if (ret == -ENODEV && bp->mii_bus) { phydev = phy_find_first(bp->mii_bus); @@ -2337,11 +2433,19 @@ static void macb_configure_dma(struct macb *bp) } } -static void macb_init_hw(struct macb *bp) +static int macb_wait_for_usx_block_lock(struct macb *bp) +{ + u32 val; + + return readx_poll_timeout(GEM_READ_USX_STATUS, bp, val, + val & GEM_BIT(USX_BLOCK_LOCK), + 1, MACB_USX_BLOCK_LOCK_TIMEOUT); +} + +static int macb_init_hw(struct macb *bp) { struct macb_queue *queue; unsigned int q; - u32 config; macb_reset_hw(bp); @@ -2375,6 +2479,23 @@ static void macb_init_hw(struct macb *bp) if (bp->caps & MACB_CAPS_JUMBO) bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + gem_writel(bp, NCR, gem_readl(bp, NCR) | + GEM_BIT(ENABLE_HS_MAC)); + gem_writel(bp, NCFGR, gem_readl(bp, NCFGR) | + MACB_BIT(FD) | GEM_BIT(PCSSEL)); + config = gem_readl(bp, USX_CONTROL); + config = GEM_BFINS(SERDES_RATE, bp->serdes_rate, config); + config &= ~GEM_BIT(TX_SCR_BYPASS); + config &= ~GEM_BIT(RX_SCR_BYPASS); + gem_writel(bp, USX_CONTROL, config | + GEM_BIT(TX_EN)); + config = gem_readl(bp, USX_CONTROL); + gem_writel(bp, USX_CONTROL, config | GEM_BIT(SIGNAL_OK)); + if (macb_wait_for_usx_block_lock(bp) < 0) + return -ETIMEDOUT; + } + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { @@ -2410,6 +2531,7 @@ static void macb_init_hw(struct macb *bp) /* Enable TX and RX */ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); + return 0; } /* The hash address register is 64 bits long and takes up two @@ -2568,7 +2690,9 @@ static int macb_open(struct net_device *dev) napi_enable(&queue->napi); bp->macbgem_ops.mog_init_rings(bp); - macb_init_hw(bp); + err = macb_init_hw(bp); + if (err) + goto init_hw_exit; /* schedule a link state check */ phylink_start(bp->pl); @@ -2578,6 +2702,9 @@ static int macb_open(struct net_device *dev) if (bp->ptp_info) bp->ptp_info->ptp_init(dev); +init_hw_exit: + if (err) + macb_free_consistent(bp); pm_exit: if (err) { pm_runtime_put_sync(&bp->pdev->dev); @@ -3493,6 +3620,9 @@ static void macb_configure_caps(struct macb *bp, default: break; } + dcfg = gem_readl(bp, DCFG12); + if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) + bp->caps |= MACB_CAPS_HIGH_SPEED; dcfg = gem_readl(bp, DCFG2); if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) bp->caps |= MACB_CAPS_FIFO_MODE; @@ -3784,7 +3914,12 @@ static int macb_init(struct platform_device *pdev) if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII || bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) - val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); + val |= GEM_BIT(SGMIIEN); + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII || + bp->phy_interface == PHY_INTERFACE_MODE_SGMII || + bp->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) + val |= GEM_BIT(PCSSEL); macb_writel(bp, NCFGR, val); return 0; @@ -4372,7 +4507,21 @@ static int macb_probe(struct platform_device *pdev) } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) { u32 interface_supported = 1; - if (err == PHY_INTERFACE_MODE_SGMII || + if (err == PHY_INTERFACE_MODE_USXGMII) { + if (!(bp->caps & MACB_CAPS_HIGH_SPEED && + bp->caps & MACB_CAPS_PCS)) + interface_supported = 0; + + if (of_property_read_u32(np, "serdes-rate", + &bp->serdes_rate)) { + netdev_err(dev, + "GEM serdes_rate not specified"); + interface_supported = 0; + } + if (of_property_read_u32(np, "fixed-speed", + &bp->fixed_speed)) + bp->fixed_speed = SPEED_UNKNOWN; + } else if (err == PHY_INTERFACE_MODE_SGMII || err == PHY_INTERFACE_MODE_1000BASEX || err == PHY_INTERFACE_MODE_2500BASEX) { if (!(bp->caps & MACB_CAPS_PCS)) From patchwork Sun Jun 16 07:05:28 2019 Content-Type: text/plain; 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Ip=[199.43.4.28]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR07MB6976 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-16_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906160068 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org New parameters added to Cadence ethernet controller DT binding for USXGMII interface. Signed-off-by: Parshuram Thombare --- Documentation/devicetree/bindings/net/macb.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 9c5e94482b5f..cd79ec9dddfb 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -25,6 +25,10 @@ Required properties: Optional elements: 'rx_clk' applies to cdns,zynqmp-gem Optional elements: 'tsu_clk' - clocks: Phandles to input clocks. +- serdes-rate External serdes rate.Mandatory for USXGMII mode. + 0 - 5G + 1 - 10G +- fixed-speed Speed for fixed mode UXSGMII interface based link The MAC address will be determined using the optional properties defined in ethernet.txt.