From patchwork Fri Jun 14 10:40:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1115893 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45QHDV5SKlz9sBb for ; Fri, 14 Jun 2019 20:39:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727298AbfFNKjP (ORCPT ); Fri, 14 Jun 2019 06:39:15 -0400 Received: from inva021.nxp.com ([92.121.34.21]:36034 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727141AbfFNKjN (ORCPT ); Fri, 14 Jun 2019 06:39:13 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id BCFD12003DA; Fri, 14 Jun 2019 12:39:11 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3C9E0200E7C; Fri, 14 Jun 2019 12:39:07 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 451ED4029F; Fri, 14 Jun 2019 18:39:01 +0800 (SGT) From: Yangbo Lu To: netdev@vger.kernel.org, "David S . Miller" , Richard Cochran , Rob Herring , Shawn Guo , Andrew Lunn Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Yangbo Lu Subject: [v2, 1/6] ptp: add QorIQ PTP support for DPAA2 Date: Fri, 14 Jun 2019 18:40:50 +0800 Message-Id: <20190614104055.43998-2-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614104055.43998-1-yangbo.lu@nxp.com> References: <20190614104055.43998-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch is to add QorIQ PTP support for DPAA2. Although dpaa2-ptp.c driver is a fsl_mc_driver which is using MC APIs for register accessing, it's same IP block with eTSEC/DPAA/ENETC 1588 timer. We will convert to reuse ptp_qoriq driver by using register ioremap and dropping related MC APIs. Also allow to compile ptp_qoriq with COMPILE_TEST. Signed-off-by: Yangbo Lu --- Changes for v2: - Allowed to compile with COMPILE_TEST. --- drivers/ptp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig index 9b8fee5..960961f 100644 --- a/drivers/ptp/Kconfig +++ b/drivers/ptp/Kconfig @@ -44,7 +44,7 @@ config PTP_1588_CLOCK_DTE config PTP_1588_CLOCK_QORIQ tristate "Freescale QorIQ 1588 timer as PTP clock" - depends on GIANFAR || FSL_DPAA_ETH || FSL_ENETC || FSL_ENETC_VF + depends on GIANFAR || FSL_DPAA_ETH || FSL_DPAA2_ETH || FSL_ENETC || FSL_ENETC_VF || COMPILE_TEST depends on PTP_1588_CLOCK default y help From patchwork Fri Jun 14 10:40:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1115894 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45QHDW5wkFz9sNl for ; Fri, 14 Jun 2019 20:39:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727568AbfFNKjv (ORCPT ); Fri, 14 Jun 2019 06:39:51 -0400 Received: from inva021.nxp.com ([92.121.34.21]:36076 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726784AbfFNKjP (ORCPT ); Fri, 14 Jun 2019 06:39:15 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 539C4200E7C; Fri, 14 Jun 2019 12:39:13 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9710D200E7F; Fri, 14 Jun 2019 12:39:08 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 6EE5F402DD; Fri, 14 Jun 2019 18:39:02 +0800 (SGT) From: Yangbo Lu To: netdev@vger.kernel.org, "David S . Miller" , Richard Cochran , Rob Herring , Shawn Guo , Andrew Lunn Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Yangbo Lu Subject: [v2, 2/6] dpaa2-ptp: reuse ptp_qoriq driver Date: Fri, 14 Jun 2019 18:40:51 +0800 Message-Id: <20190614104055.43998-3-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614104055.43998-1-yangbo.lu@nxp.com> References: <20190614104055.43998-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Although dpaa2-ptp.c driver is a fsl_mc_driver which is using MC APIs for register accessing, it's same IP block with eTSEC/DPAA/ENETC 1588 timer. This patch is to convert to reuse ptp_qoriq driver by using register ioremap and dropping related MC APIs. However the interrupts could only be handled by MC which fires MSIs to ARM cores. So the interrupt enabling and handling still rely on MC APIs. Signed-off-by: Yangbo Lu --- Changes for v2: - None. --- drivers/net/ethernet/freescale/dpaa2/Kconfig | 3 +- drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c | 160 +++++------------------ drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h | 13 -- drivers/net/ethernet/freescale/dpaa2/dprtc.c | 120 ----------------- drivers/net/ethernet/freescale/dpaa2/dprtc.h | 20 --- 5 files changed, 34 insertions(+), 282 deletions(-) diff --git a/drivers/net/ethernet/freescale/dpaa2/Kconfig b/drivers/net/ethernet/freescale/dpaa2/Kconfig index 8bd3847..fbef282 100644 --- a/drivers/net/ethernet/freescale/dpaa2/Kconfig +++ b/drivers/net/ethernet/freescale/dpaa2/Kconfig @@ -10,8 +10,7 @@ config FSL_DPAA2_ETH config FSL_DPAA2_PTP_CLOCK tristate "Freescale DPAA2 PTP Clock" - depends on FSL_DPAA2_ETH - imply PTP_1588_CLOCK + depends on FSL_DPAA2_ETH && PTP_1588_CLOCK_QORIQ default y help This driver adds support for using the DPAA2 1588 timer module diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c index 9b150db..6c57e17 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c @@ -5,114 +5,14 @@ */ #include -#include -#include +#include +#include #include +#include #include "dpaa2-ptp.h" -struct ptp_dpaa2_priv { - struct fsl_mc_device *ptp_mc_dev; - struct ptp_clock *clock; - struct ptp_clock_info caps; - u32 freq_comp; -}; - -/* PTP clock operations */ -static int ptp_dpaa2_adjfreq(struct ptp_clock_info *ptp, s32 ppb) -{ - struct ptp_dpaa2_priv *ptp_dpaa2 = - container_of(ptp, struct ptp_dpaa2_priv, caps); - struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev; - struct device *dev = &mc_dev->dev; - u64 adj; - u32 diff, tmr_add; - int neg_adj = 0; - int err = 0; - - if (ppb < 0) { - neg_adj = 1; - ppb = -ppb; - } - - tmr_add = ptp_dpaa2->freq_comp; - adj = tmr_add; - adj *= ppb; - diff = div_u64(adj, 1000000000ULL); - - tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff; - - err = dprtc_set_freq_compensation(mc_dev->mc_io, 0, - mc_dev->mc_handle, tmr_add); - if (err) - dev_err(dev, "dprtc_set_freq_compensation err %d\n", err); - return err; -} - -static int ptp_dpaa2_adjtime(struct ptp_clock_info *ptp, s64 delta) -{ - struct ptp_dpaa2_priv *ptp_dpaa2 = - container_of(ptp, struct ptp_dpaa2_priv, caps); - struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev; - struct device *dev = &mc_dev->dev; - s64 now; - int err = 0; - - err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &now); - if (err) { - dev_err(dev, "dprtc_get_time err %d\n", err); - return err; - } - - now += delta; - - err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, now); - if (err) - dev_err(dev, "dprtc_set_time err %d\n", err); - return err; -} - -static int ptp_dpaa2_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) -{ - struct ptp_dpaa2_priv *ptp_dpaa2 = - container_of(ptp, struct ptp_dpaa2_priv, caps); - struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev; - struct device *dev = &mc_dev->dev; - u64 ns; - u32 remainder; - int err = 0; - - err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &ns); - if (err) { - dev_err(dev, "dprtc_get_time err %d\n", err); - return err; - } - - ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); - ts->tv_nsec = remainder; - return err; -} - -static int ptp_dpaa2_settime(struct ptp_clock_info *ptp, - const struct timespec64 *ts) -{ - struct ptp_dpaa2_priv *ptp_dpaa2 = - container_of(ptp, struct ptp_dpaa2_priv, caps); - struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev; - struct device *dev = &mc_dev->dev; - u64 ns; - int err = 0; - - ns = ts->tv_sec * 1000000000ULL; - ns += ts->tv_nsec; - - err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, ns); - if (err) - dev_err(dev, "dprtc_set_time err %d\n", err); - return err; -} - -static const struct ptp_clock_info ptp_dpaa2_caps = { +static const struct ptp_clock_info dpaa2_ptp_caps = { .owner = THIS_MODULE, .name = "DPAA2 PTP Clock", .max_adj = 512000, @@ -121,21 +21,22 @@ static const struct ptp_clock_info ptp_dpaa2_caps = { .n_per_out = 3, .n_pins = 0, .pps = 1, - .adjfreq = ptp_dpaa2_adjfreq, - .adjtime = ptp_dpaa2_adjtime, - .gettime64 = ptp_dpaa2_gettime, - .settime64 = ptp_dpaa2_settime, + .adjfine = ptp_qoriq_adjfine, + .adjtime = ptp_qoriq_adjtime, + .gettime64 = ptp_qoriq_gettime, + .settime64 = ptp_qoriq_settime, }; static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev) { struct device *dev = &mc_dev->dev; - struct ptp_dpaa2_priv *ptp_dpaa2; - u32 tmr_add = 0; + struct ptp_qoriq *ptp_qoriq; + struct device_node *node; + void __iomem *base; int err; - ptp_dpaa2 = devm_kzalloc(dev, sizeof(*ptp_dpaa2), GFP_KERNEL); - if (!ptp_dpaa2) + ptp_qoriq = devm_kzalloc(dev, sizeof(*ptp_qoriq), GFP_KERNEL); + if (!ptp_qoriq) return -ENOMEM; err = fsl_mc_portal_allocate(mc_dev, 0, &mc_dev->mc_io); @@ -154,30 +55,33 @@ static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev) goto err_free_mcp; } - ptp_dpaa2->ptp_mc_dev = mc_dev; + ptp_qoriq->dev = dev; - err = dprtc_get_freq_compensation(mc_dev->mc_io, 0, - mc_dev->mc_handle, &tmr_add); - if (err) { - dev_err(dev, "dprtc_get_freq_compensation err %d\n", err); + node = of_find_compatible_node(NULL, NULL, "fsl,dpaa2-ptp"); + if (!node) { + err = -ENODEV; goto err_close; } - ptp_dpaa2->freq_comp = tmr_add; - ptp_dpaa2->caps = ptp_dpaa2_caps; + dev->of_node = node; - ptp_dpaa2->clock = ptp_clock_register(&ptp_dpaa2->caps, dev); - if (IS_ERR(ptp_dpaa2->clock)) { - err = PTR_ERR(ptp_dpaa2->clock); + base = of_iomap(node, 0); + if (!base) { + err = -ENOMEM; goto err_close; } - dpaa2_phc_index = ptp_clock_index(ptp_dpaa2->clock); + err = ptp_qoriq_init(ptp_qoriq, base, &dpaa2_ptp_caps); + if (err) + goto err_unmap; - dev_set_drvdata(dev, ptp_dpaa2); + dpaa2_phc_index = ptp_qoriq->phc_index; + dev_set_drvdata(dev, ptp_qoriq); return 0; +err_unmap: + iounmap(base); err_close: dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); err_free_mcp: @@ -188,11 +92,13 @@ static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev) static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) { - struct ptp_dpaa2_priv *ptp_dpaa2; struct device *dev = &mc_dev->dev; + struct ptp_qoriq *ptp_qoriq; + + ptp_qoriq = dev_get_drvdata(dev); - ptp_dpaa2 = dev_get_drvdata(dev); - ptp_clock_unregister(ptp_dpaa2->clock); + dpaa2_phc_index = -1; + ptp_qoriq_free(ptp_qoriq); dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); fsl_mc_portal_free(mc_dev->mc_io); diff --git a/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h b/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h index 9af4ac7..dd74aa9 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h +++ b/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h @@ -17,24 +17,11 @@ #define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800) #define DPRTC_CMDID_OPEN DPRTC_CMD(0x810) -#define DPRTC_CMDID_SET_FREQ_COMPENSATION DPRTC_CMD(0x1d1) -#define DPRTC_CMDID_GET_FREQ_COMPENSATION DPRTC_CMD(0x1d2) -#define DPRTC_CMDID_GET_TIME DPRTC_CMD(0x1d3) -#define DPRTC_CMDID_SET_TIME DPRTC_CMD(0x1d4) - #pragma pack(push, 1) struct dprtc_cmd_open { __le32 dprtc_id; }; -struct dprtc_get_freq_compensation { - __le32 freq_compensation; -}; - -struct dprtc_time { - __le64 time; -}; - #pragma pack(pop) #endif /* _FSL_DPRTC_CMD_H */ diff --git a/drivers/net/ethernet/freescale/dpaa2/dprtc.c b/drivers/net/ethernet/freescale/dpaa2/dprtc.c index c13e09b..1ae303e 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dprtc.c +++ b/drivers/net/ethernet/freescale/dpaa2/dprtc.c @@ -72,123 +72,3 @@ int dprtc_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } - -/** - * dprtc_set_freq_compensation() - Sets a new frequency compensation value. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRTC object - * @freq_compensation: The new frequency compensation value to set. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u32 freq_compensation) -{ - struct dprtc_get_freq_compensation *cmd_params; - struct fsl_mc_command cmd = { 0 }; - - cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_FREQ_COMPENSATION, - cmd_flags, - token); - cmd_params = (struct dprtc_get_freq_compensation *)cmd.params; - cmd_params->freq_compensation = cpu_to_le32(freq_compensation); - - return mc_send_command(mc_io, &cmd); -} - -/** - * dprtc_get_freq_compensation() - Retrieves the frequency compensation value - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRTC object - * @freq_compensation: Frequency compensation value - * - * Return: '0' on Success; Error code otherwise. - */ -int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u32 *freq_compensation) -{ - struct dprtc_get_freq_compensation *rsp_params; - struct fsl_mc_command cmd = { 0 }; - int err; - - cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_FREQ_COMPENSATION, - cmd_flags, - token); - - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - rsp_params = (struct dprtc_get_freq_compensation *)cmd.params; - *freq_compensation = le32_to_cpu(rsp_params->freq_compensation); - - return 0; -} - -/** - * dprtc_get_time() - Returns the current RTC time. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRTC object - * @time: Current RTC time. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprtc_get_time(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - uint64_t *time) -{ - struct dprtc_time *rsp_params; - struct fsl_mc_command cmd = { 0 }; - int err; - - cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_TIME, - cmd_flags, - token); - - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - rsp_params = (struct dprtc_time *)cmd.params; - *time = le64_to_cpu(rsp_params->time); - - return 0; -} - -/** - * dprtc_set_time() - Updates current RTC time. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRTC object - * @time: New RTC time. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprtc_set_time(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - uint64_t time) -{ - struct dprtc_time *cmd_params; - struct fsl_mc_command cmd = { 0 }; - - cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_TIME, - cmd_flags, - token); - cmd_params = (struct dprtc_time *)cmd.params; - cmd_params->time = cpu_to_le64(time); - - return mc_send_command(mc_io, &cmd); -} diff --git a/drivers/net/ethernet/freescale/dpaa2/dprtc.h b/drivers/net/ethernet/freescale/dpaa2/dprtc.h index fe19618..c2d508b 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dprtc.h +++ b/drivers/net/ethernet/freescale/dpaa2/dprtc.h @@ -22,24 +22,4 @@ int dprtc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u32 freq_compensation); - -int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u32 *freq_compensation); - -int dprtc_get_time(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - uint64_t *time); - -int dprtc_set_time(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - uint64_t time); - #endif /* __FSL_DPRTC_H */ From patchwork Fri Jun 14 10:40:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1115891 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45QHD83jkYz9s9y for ; Fri, 14 Jun 2019 20:39:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727347AbfFNKjR (ORCPT ); Fri, 14 Jun 2019 06:39:17 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55722 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727251AbfFNKjQ (ORCPT ); Fri, 14 Jun 2019 06:39:16 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 163F21A0631; Fri, 14 Jun 2019 12:39:14 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8A8521A061A; Fri, 14 Jun 2019 12:39:09 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C82DE40310; Fri, 14 Jun 2019 18:39:03 +0800 (SGT) From: Yangbo Lu To: netdev@vger.kernel.org, "David S . Miller" , Richard Cochran , Rob Herring , Shawn Guo , Andrew Lunn Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Yangbo Lu Subject: [v2, 3/6] dt-binding: ptp_qoriq: support DPAA2 PTP compatible Date: Fri, 14 Jun 2019 18:40:52 +0800 Message-Id: <20190614104055.43998-4-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614104055.43998-1-yangbo.lu@nxp.com> References: <20190614104055.43998-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add a new compatible for DPAA2 PTP. Signed-off-by: Yangbo Lu --- Changes for v2: - None. --- Documentation/devicetree/bindings/ptp/ptp-qoriq.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt index 6ec0534..d48f9eb 100644 --- a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt +++ b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt @@ -4,7 +4,8 @@ General Properties: - compatible Should be "fsl,etsec-ptp" for eTSEC Should be "fsl,fman-ptp-timer" for DPAA FMan - Should be "fsl,enetc-ptp" for ENETC + Should be "fsl,dpaa2-ptp" for DPAA2 + Should be "fsl,enetc-ptp" for ENETC - reg Offset and length of the register set for the device - interrupts There should be at least two interrupts. Some devices have as many as four PTP related interrupts. From patchwork Fri Jun 14 10:40:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1115892 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45QHD863YDz9sBb for ; Fri, 14 Jun 2019 20:39:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727517AbfFNKjf (ORCPT ); Fri, 14 Jun 2019 06:39:35 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55750 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727315AbfFNKjR (ORCPT ); Fri, 14 Jun 2019 06:39:17 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 382FC1A0630; Fri, 14 Jun 2019 12:39:15 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id AC2021A062D; Fri, 14 Jun 2019 12:39:10 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 27329402A0; Fri, 14 Jun 2019 18:39:05 +0800 (SGT) From: Yangbo Lu To: netdev@vger.kernel.org, "David S . Miller" , Richard Cochran , Rob Herring , Shawn Guo , Andrew Lunn Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Yangbo Lu Subject: [v2, 4/6] arm64: dts: fsl: add ptp timer node for dpaa2 platforms Date: Fri, 14 Jun 2019 18:40:53 +0800 Message-Id: <20190614104055.43998-5-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614104055.43998-1-yangbo.lu@nxp.com> References: <20190614104055.43998-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch is to add ptp timer device tree node for dpaa2 platforms(ls1088a/ls208xa/lx2160a). Signed-off-by: Yangbo Lu --- Changes for v2: - None. --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 661137f..dacd8cf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -609,6 +609,14 @@ ; }; + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen 4 0>; + little-endian; + fsl,extts-fifo; + }; + cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index d7e78dc..3ace919 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -321,6 +321,14 @@ }; }; + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen 4 1>; + little-endian; + fsl,extts-fifo; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 125a8cc..e6fdba3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -848,6 +848,14 @@ dma-coherent; }; + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen 4 1>; + little-endian; + fsl,extts-fifo; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, From patchwork Fri Jun 14 10:40:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1115889 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45QHCv5mMXz9sBb for ; Fri, 14 Jun 2019 20:39:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727461AbfFNKjW (ORCPT ); Fri, 14 Jun 2019 06:39:22 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55802 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727365AbfFNKjT (ORCPT ); Fri, 14 Jun 2019 06:39:19 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3BAB41A061A; Fri, 14 Jun 2019 12:39:17 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7DCEB1A0629; Fri, 14 Jun 2019 12:39:12 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 4BE6140319; Fri, 14 Jun 2019 18:39:06 +0800 (SGT) From: Yangbo Lu To: netdev@vger.kernel.org, "David S . Miller" , Richard Cochran , Rob Herring , Shawn Guo , Andrew Lunn Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Yangbo Lu Subject: [v2, 5/6] dpaa2-ptp: add interrupt support Date: Fri, 14 Jun 2019 18:40:54 +0800 Message-Id: <20190614104055.43998-6-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614104055.43998-1-yangbo.lu@nxp.com> References: <20190614104055.43998-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch is to add interrupt support for dpaa2 ptp clock, including MC APIs and PPS interrupt support. Other events haven't been supported in MC by now. Signed-off-by: Yangbo Lu --- Changes for v2: - None. --- drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c | 110 +++++++++++- drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h | 45 +++++ drivers/net/ethernet/freescale/dpaa2/dprtc.c | 219 +++++++++++++++++++++++ drivers/net/ethernet/freescale/dpaa2/dprtc.h | 44 +++++ 4 files changed, 417 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c index 6c57e17..a9503ae 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c @@ -7,11 +7,55 @@ #include #include #include +#include #include #include #include "dpaa2-ptp.h" +static int dpaa2_ptp_enable(struct ptp_clock_info *ptp, + struct ptp_clock_request *rq, int on) +{ + struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps); + struct fsl_mc_device *mc_dev; + struct device *dev; + u32 mask = 0; + u32 bit; + int err; + + dev = ptp_qoriq->dev; + mc_dev = to_fsl_mc_device(dev); + + switch (rq->type) { + case PTP_CLK_REQ_PPS: + bit = DPRTC_EVENT_PPS; + break; + default: + return -EOPNOTSUPP; + } + + err = dprtc_get_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, + DPRTC_IRQ_INDEX, &mask); + if (err < 0) { + dev_err(dev, "dprtc_get_irq_mask(): %d\n", err); + return err; + } + + if (on) + mask |= bit; + else + mask &= ~bit; + + err = dprtc_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, + DPRTC_IRQ_INDEX, mask); + if (err < 0) { + dev_err(dev, "dprtc_set_irq_mask(): %d\n", err); + return err; + } + + return 0; +} + static const struct ptp_clock_info dpaa2_ptp_caps = { .owner = THIS_MODULE, .name = "DPAA2 PTP Clock", @@ -25,11 +69,47 @@ static const struct ptp_clock_info dpaa2_ptp_caps = { .adjtime = ptp_qoriq_adjtime, .gettime64 = ptp_qoriq_gettime, .settime64 = ptp_qoriq_settime, + .enable = dpaa2_ptp_enable, }; +static irqreturn_t dpaa2_ptp_irq_handler_thread(int irq, void *priv) +{ + struct ptp_qoriq *ptp_qoriq = priv; + struct ptp_clock_event event; + struct fsl_mc_device *mc_dev; + struct device *dev; + u32 status = 0; + int err; + + dev = ptp_qoriq->dev; + mc_dev = to_fsl_mc_device(dev); + + err = dprtc_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, + DPRTC_IRQ_INDEX, &status); + if (unlikely(err)) { + dev_err(dev, "dprtc_get_irq_status err %d\n", err); + return IRQ_NONE; + } + + if (status & DPRTC_EVENT_PPS) { + event.type = PTP_CLOCK_PPS; + ptp_clock_event(ptp_qoriq->clock, &event); + } + + err = dprtc_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, + DPRTC_IRQ_INDEX, status); + if (unlikely(err)) { + dev_err(dev, "dprtc_clear_irq_status err %d\n", err); + return IRQ_NONE; + } + + return IRQ_HANDLED; +} + static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev) { struct device *dev = &mc_dev->dev; + struct fsl_mc_device_irq *irq; struct ptp_qoriq *ptp_qoriq; struct device_node *node; void __iomem *base; @@ -71,15 +151,42 @@ static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev) goto err_close; } + err = fsl_mc_allocate_irqs(mc_dev); + if (err) { + dev_err(dev, "MC irqs allocation failed\n"); + goto err_unmap; + } + + irq = mc_dev->irqs[0]; + ptp_qoriq->irq = irq->msi_desc->irq; + + err = devm_request_threaded_irq(dev, ptp_qoriq->irq, NULL, + dpaa2_ptp_irq_handler_thread, + IRQF_NO_SUSPEND | IRQF_ONESHOT, + dev_name(dev), ptp_qoriq); + if (err < 0) { + dev_err(dev, "devm_request_threaded_irq(): %d\n", err); + goto err_free_mc_irq; + } + + err = dprtc_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, + DPRTC_IRQ_INDEX, 1); + if (err < 0) { + dev_err(dev, "dprtc_set_irq_enable(): %d\n", err); + goto err_free_mc_irq; + } + err = ptp_qoriq_init(ptp_qoriq, base, &dpaa2_ptp_caps); if (err) - goto err_unmap; + goto err_free_mc_irq; dpaa2_phc_index = ptp_qoriq->phc_index; dev_set_drvdata(dev, ptp_qoriq); return 0; +err_free_mc_irq: + fsl_mc_free_irqs(mc_dev); err_unmap: iounmap(base); err_close: @@ -100,6 +207,7 @@ static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) dpaa2_phc_index = -1; ptp_qoriq_free(ptp_qoriq); + fsl_mc_free_irqs(mc_dev); dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); fsl_mc_portal_free(mc_dev->mc_io); diff --git a/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h b/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h index dd74aa9..720cd50 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h +++ b/drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h @@ -17,11 +17,56 @@ #define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800) #define DPRTC_CMDID_OPEN DPRTC_CMD(0x810) +#define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012) +#define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013) +#define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD(0x014) +#define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015) +#define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016) +#define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017) + #pragma pack(push, 1) struct dprtc_cmd_open { __le32 dprtc_id; }; +struct dprtc_cmd_get_irq { + __le32 pad; + u8 irq_index; +}; + +struct dprtc_cmd_set_irq_enable { + u8 en; + u8 pad[3]; + u8 irq_index; +}; + +struct dprtc_rsp_get_irq_enable { + u8 en; +}; + +struct dprtc_cmd_set_irq_mask { + __le32 mask; + u8 irq_index; +}; + +struct dprtc_rsp_get_irq_mask { + __le32 mask; +}; + +struct dprtc_cmd_get_irq_status { + __le32 status; + u8 irq_index; +}; + +struct dprtc_rsp_get_irq_status { + __le32 status; +}; + +struct dprtc_cmd_clear_irq_status { + __le32 status; + u8 irq_index; +}; + #pragma pack(pop) #endif /* _FSL_DPRTC_CMD_H */ diff --git a/drivers/net/ethernet/freescale/dpaa2/dprtc.c b/drivers/net/ethernet/freescale/dpaa2/dprtc.c index 1ae303e..ed52a34 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dprtc.c +++ b/drivers/net/ethernet/freescale/dpaa2/dprtc.c @@ -72,3 +72,222 @@ int dprtc_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } + +/** + * dprtc_set_irq_enable() - Set overall interrupt state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRTC object + * @irq_index: The interrupt index to configure + * @en: Interrupt state - enable = 1, disable = 0 + * + * Allows GPP software to control when interrupts are generated. + * Each interrupt can have up to 32 causes. The enable/disable control's the + * overall interrupt state. if the interrupt is disabled no causes will cause + * an interrupt. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprtc_set_irq_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u8 en) +{ + struct dprtc_cmd_set_irq_enable *cmd_params; + struct fsl_mc_command cmd = { 0 }; + + cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dprtc_cmd_set_irq_enable *)cmd.params; + cmd_params->irq_index = irq_index; + cmd_params->en = en; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dprtc_get_irq_enable() - Get overall interrupt state + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRTC object + * @irq_index: The interrupt index to configure + * @en: Returned interrupt state - enable = 1, disable = 0 + * + * Return: '0' on Success; Error code otherwise. + */ +int dprtc_get_irq_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u8 *en) +{ + struct dprtc_rsp_get_irq_enable *rsp_params; + struct dprtc_cmd_get_irq *cmd_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dprtc_cmd_get_irq *)cmd.params; + cmd_params->irq_index = irq_index; + + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dprtc_rsp_get_irq_enable *)cmd.params; + *en = rsp_params->en; + + return 0; +} + +/** + * dprtc_set_irq_mask() - Set interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRTC object + * @irq_index: The interrupt index to configure + * @mask: Event mask to trigger interrupt; + * each bit: + * 0 = ignore event + * 1 = consider event for asserting IRQ + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on Success; Error code otherwise. + */ +int dprtc_set_irq_mask(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 mask) +{ + struct dprtc_cmd_set_irq_mask *cmd_params; + struct fsl_mc_command cmd = { 0 }; + + cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dprtc_cmd_set_irq_mask *)cmd.params; + cmd_params->mask = cpu_to_le32(mask); + cmd_params->irq_index = irq_index; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dprtc_get_irq_mask() - Get interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRTC object + * @irq_index: The interrupt index to configure + * @mask: Returned event mask to trigger interrupt + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on Success; Error code otherwise. + */ +int dprtc_get_irq_mask(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 *mask) +{ + struct dprtc_rsp_get_irq_mask *rsp_params; + struct dprtc_cmd_get_irq *cmd_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dprtc_cmd_get_irq *)cmd.params; + cmd_params->irq_index = irq_index; + + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dprtc_rsp_get_irq_mask *)cmd.params; + *mask = le32_to_cpu(rsp_params->mask); + + return 0; +} + +/** + * dprtc_get_irq_status() - Get the current status of any pending interrupts. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRTC object + * @irq_index: The interrupt index to configure + * @status: Returned interrupts status - one bit per cause: + * 0 = no interrupt pending + * 1 = interrupt pending + * + * Return: '0' on Success; Error code otherwise. + */ +int dprtc_get_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 *status) +{ + struct dprtc_cmd_get_irq_status *cmd_params; + struct dprtc_rsp_get_irq_status *rsp_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dprtc_cmd_get_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(*status); + cmd_params->irq_index = irq_index; + + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dprtc_rsp_get_irq_status *)cmd.params; + *status = le32_to_cpu(rsp_params->status); + + return 0; +} + +/** + * dprtc_clear_irq_status() - Clear a pending interrupt's status + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRTC object + * @irq_index: The interrupt index to configure + * @status: Bits to clear (W1C) - one bit per cause: + * 0 = don't change + * 1 = clear status bit + * + * Return: '0' on Success; Error code otherwise. + */ +int dprtc_clear_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 status) +{ + struct dprtc_cmd_clear_irq_status *cmd_params; + struct fsl_mc_command cmd = { 0 }; + + cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLEAR_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dprtc_cmd_clear_irq_status *)cmd.params; + cmd_params->irq_index = irq_index; + cmd_params->status = cpu_to_le32(status); + + return mc_send_command(mc_io, &cmd); +} diff --git a/drivers/net/ethernet/freescale/dpaa2/dprtc.h b/drivers/net/ethernet/freescale/dpaa2/dprtc.h index c2d508b..be7914c 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dprtc.h +++ b/drivers/net/ethernet/freescale/dpaa2/dprtc.h @@ -13,6 +13,14 @@ struct fsl_mc_io; +/** + * Number of irq's + */ +#define DPRTC_MAX_IRQ_NUM 1 +#define DPRTC_IRQ_INDEX 0 + +#define DPRTC_EVENT_PPS 0x08000000 + int dprtc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dprtc_id, @@ -22,4 +30,40 @@ int dprtc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dprtc_set_irq_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u8 en); + +int dprtc_get_irq_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u8 *en); + +int dprtc_set_irq_mask(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 mask); + +int dprtc_get_irq_mask(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 *mask); + +int dprtc_get_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 *status); + +int dprtc_clear_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 status); + #endif /* __FSL_DPRTC_H */ From patchwork Fri Jun 14 10:40:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1115890 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45QHD33Y53z9sBb for ; Fri, 14 Jun 2019 20:39:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727435AbfFNKjU (ORCPT ); Fri, 14 Jun 2019 06:39:20 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55840 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727387AbfFNKjT (ORCPT ); Fri, 14 Jun 2019 06:39:19 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 24EC01A0631; Fri, 14 Jun 2019 12:39:18 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 999711A062F; Fri, 14 Jun 2019 12:39:13 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 81D1E4031C; Fri, 14 Jun 2019 18:39:07 +0800 (SGT) From: Yangbo Lu To: netdev@vger.kernel.org, "David S . Miller" , Richard Cochran , Rob Herring , Shawn Guo , Andrew Lunn Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Yangbo Lu Subject: [v2, 6/6] MAINTAINERS: maintain DPAA2 PTP driver in QorIQ PTP entry Date: Fri, 14 Jun 2019 18:40:55 +0800 Message-Id: <20190614104055.43998-7-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614104055.43998-1-yangbo.lu@nxp.com> References: <20190614104055.43998-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Maintain DPAA2 PTP driver in QorIQ PTP entry. Signed-off-by: Yangbo Lu --- Changes for v2: - None. --- MAINTAINERS | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b70d5d5..b1f2207 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4922,13 +4922,6 @@ L: linux-kernel@vger.kernel.org S: Maintained F: drivers/staging/fsl-dpaa2/ethsw -DPAA2 PTP CLOCK DRIVER -M: Yangbo Lu -L: netdev@vger.kernel.org -S: Maintained -F: drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp* -F: drivers/net/ethernet/freescale/dpaa2/dprtc* - DPT_I2O SCSI RAID DRIVER M: Adaptec OEM Raid Solutions L: linux-scsi@vger.kernel.org @@ -6371,6 +6364,8 @@ FREESCALE QORIQ PTP CLOCK DRIVER M: Yangbo Lu L: netdev@vger.kernel.org S: Maintained +F: drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp* +F: drivers/net/ethernet/freescale/dpaa2/dprtc* F: drivers/net/ethernet/freescale/enetc/enetc_ptp.c F: drivers/ptp/ptp_qoriq.c F: drivers/ptp/ptp_qoriq_debugfs.c