From patchwork Wed Nov 1 05:59:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 832848 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yRcyG4kt2z9sPs for ; Wed, 1 Nov 2017 17:00:22 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yRcyG2cDzzDr4H for ; Wed, 1 Nov 2017 17:00:22 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yRcy56qvZzDqlM for ; Wed, 1 Nov 2017 17:00:12 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com. (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id vA15xlvb002790; Wed, 1 Nov 2017 00:59:49 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Wed, 1 Nov 2017 16:59:43 +1100 Message-Id: <20171101055944.1792-1-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.6 Subject: [Skiboot] [PATCH v3 1/2] xive: Update inits for DD2.0 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This updates some inits based on information from the HW designers. This includes enabling some new DD2.0 features that we don't yet exploit. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 29 +++++++++++++++++++++++++++-- include/xive.h | 25 ++++++++++++++++++++----- 2 files changed, 47 insertions(+), 7 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 4fd8a301..352ad3be 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1671,9 +1671,13 @@ static bool xive_config_init(struct xive *x) #endif val |= PC_TCTXT_CHIPID_OVERRIDE; val |= PC_TCTXT_CFG_TARGET_EN; - /* Disable pressure relief as we hijack the field in the VPs */ - val &= ~PC_TCTXT_CFG_STORE_ACK; val = SETFIELD(PC_TCTXT_CHIPID, val, x->block_id); + if (x->rev >= XIVE_REV_2) { + val = SETFIELD(PC_TCTXT_INIT_AGE, val, 0x2); + val |= PC_TCTXT_CFG_LGS_EN; + /* Disable pressure relief as we hijack the field in the VPs */ + val &= ~PC_TCTXT_CFG_STORE_ACK; + } xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); @@ -1681,12 +1685,33 @@ static bool xive_config_init(struct xive *x) if (x->rev < XIVE_REV_2) return true; + val = xive_regr(x, CQ_CFG_PB_GEN); + /* 1-block-per-chip mode */ + val = SETFIELD(CQ_INT_ADDR_OPT, val, 2); + xive_regw(x, CQ_CFG_PB_GEN, val); + /* Enable StoreEOI */ val = xive_regr(x, VC_SBC_CONFIG); val |= VC_SBC_CONF_CPLX_CIST | VC_SBC_CONF_CIST_BOTH; val |= VC_SBC_CONF_NO_UPD_PRF; xive_regw(x, VC_SBC_CONFIG, val); + /* Enable block tracking */ + val = xive_regr(x, PC_TCTXT_TRACK); + val |= PC_TCTXT_TRACK_EN; + xive_regw(x, PC_TCTXT_TRACK, val); + + /* Enable relaxed ordering of trigger forwarding */ + val = xive_regr(x, VC_AIB_TX_ORDER_TAG2); + val |= VC_AIB_TX_ORDER_TAG2_REL_TF; + xive_regw(x, VC_AIB_TX_ORDER_TAG2, val); + + /* Enable new END s and u bits for silent escalate */ + val = xive_regr(x, VC_EQC_CONFIG); + val |= VC_EQC_CONF_ENABLE_END_s_BIT; + val |= VC_EQC_CONF_ENABLE_END_u_BIT; + xive_regw(x, VC_EQC_CONFIG, val); + return true; } diff --git a/include/xive.h b/include/xive.h index 70f6499f..63ee77b3 100644 --- a/include/xive.h +++ b/include/xive.h @@ -25,6 +25,7 @@ #define CQ_SWI_RSP 0x048 #define X_CQ_CFG_PB_GEN 0x0a #define CQ_CFG_PB_GEN 0x050 +#define CQ_INT_ADDR_OPT PPC_BITMASK(14,15) #define X_CQ_IC_BAR 0x10 #define X_CQ_MSGSND 0x0b #define CQ_MSGSND 0x058 @@ -75,10 +76,15 @@ #define PC_TCTXT_CFG 0x400 #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) +#define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) +#define PC_TCTXT_INIT_AGE PPC_BITMASK(30,31) +#define X_PC_TCTXT_TRACK 0x101 +#define PC_TCTXT_TRACK 0x408 +#define PC_TCTXT_TRACK_EN PPC_BIT(0) #define X_PC_TCTXT_INDIR0 0x104 #define PC_TCTXT_INDIR0 0x420 #define PC_TCTXT_INDIR_VALID PPC_BIT(0) @@ -174,6 +180,9 @@ #define VC_IRQ_CONFIG_CASCADE2 0x858 #define VC_IRQ_CONFIG_REDIST 0x860 #define VC_IRQ_CONFIG_IPI_CASC 0x868 +#define X_VC_AIB_TX_ORDER_TAG2 0x22d +#define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) +#define VC_AIB_TX_ORDER_TAG2 0x890 #define X_VC_AT_MACRO_KILL 0x23e #define VC_AT_MACRO_KILL 0x8b0 #define X_VC_AT_MACRO_KILL_MASK 0x23f @@ -196,11 +205,17 @@ #define X_VC_EQC_CWATCH_SPEC 0x215 #define VC_EQC_CONFIG 0x920 #define X_VC_EQC_CONFIG 0x214 -#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) -#define VC_EQC_CONF_SYNC_HW PPC_BIT(33) -#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) -#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) -#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) +#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) +#define VC_EQC_CONF_SYNC_HW PPC_BIT(33) +#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) +#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) +#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) +#define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) +#define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) +#define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) +#define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) +#define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) +#define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) #define VC_EQC_CWATCH_SPEC 0x928 #define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) #define VC_EQC_CWATCH_FULL PPC_BIT(8) From patchwork Wed Nov 1 05:59:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 832849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yRcyf4hTWz9sPs for ; Wed, 1 Nov 2017 17:00:42 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yRcyf3QmVzDr6D for ; Wed, 1 Nov 2017 17:00:42 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yRcy62yQpzDqvT for ; Wed, 1 Nov 2017 17:00:13 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com. (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id vA15xlvc002790; Wed, 1 Nov 2017 00:59:52 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Wed, 1 Nov 2017 16:59:44 +1100 Message-Id: <20171101055944.1792-2-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171101055944.1792-1-benh@kernel.crashing.org> References: <20171101055944.1792-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v3 2/2] xive: Fix ability to clear some EQ flags X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We could never clear "unconditional notify" and "escalate" Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 352ad3be..bb17b38a 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -4013,10 +4013,14 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, /* Always notify flag */ if (qflags & OPAL_XIVE_EQ_ALWAYS_NOTIFY) eq.w0 |= EQ_W0_UCOND_NOTIFY; + else + eq.w0 &= ~EQ_W0_UCOND_NOTIFY; /* Escalation flag */ if (qflags & OPAL_XIVE_EQ_ESCALATE) eq.w0 |= EQ_W0_ESCALATE_CTL; + else + eq.w0 &= ~EQ_W0_ESCALATE_CTL; /* Unconditionally clear the current queue pointer, set * generation to 1 and disable escalation interrupts.