From patchwork Sun Jun 2 08:01:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 1108902 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="D1YagV2w"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45GrHg4pd5z9s7h for ; Sun, 2 Jun 2019 18:01:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725953AbfFBIBf (ORCPT ); Sun, 2 Jun 2019 04:01:35 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45226 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726032AbfFBIBe (ORCPT ); Sun, 2 Jun 2019 04:01:34 -0400 Received: by mail-wr1-f66.google.com with SMTP id b18so9150550wrq.12 for ; Sun, 02 Jun 2019 01:01:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=19JHlpBM08NaaoHMsfAWuVL8kWvPtpcvA1ACdpeOftw=; b=D1YagV2wbPbvYWZG6MzOREWRKQGhvSfaNMR6MaRpuTG3+iRMDz8IOAruUW8V/2CsOV dWr/OLZLPLXOS1ERStSTQ19mZ53xlDQFlCJOUKK8RJwaNcJpCG+KarzUiCyGZMQXpEIu FrBKvFBcPrSGmn+reOALH9WfV1FPfwlGjHpjwpBngwFOMGCXiQBEKv5uQkawr3ERKQdC /qUujjIVeGUijZJ+vZVg5y/1BqUbnG5ZHp4iAUZp0E30WUPtCT7Hb3CzQFd7FOATQ1wJ 4drT05q/92szPLAyQN6niHi0Skv8EP3tySB0tavCnhXN1cXgLJpaPi7XM/05hHIDrWaj +3Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=19JHlpBM08NaaoHMsfAWuVL8kWvPtpcvA1ACdpeOftw=; b=ZzZ1d0p8dwSyWZp+UbRwgUSy6QXQDz4Jmvbclt7UduGDSY8hzRfApr0a7Hw34rxk3q BNsoG1WqGDYUAubtFM732Jq+da7BBzKIdBMb1LSG0MHuqH+p+Qfme4Jp3JZs6KS/hwXa 7m+f0Mo/zgXBliyGR+biC0ufYxuT0JN5BijUCkui4L3el4znQ4fqZDUahjfkqTxucNSC rgnx+EcZiO7FLL7vszHNYm3T097XcCqupiEhLk/+oMwSUsbtkPRGI2OC5suw4iN+Y3C9 F3V0wDMO4cZNg9OtH/rQ1eAYSDkcs8ddYC375MM+GXZ/7KH2CZLZmEIPIREIxCqLTVve 3+pg== X-Gm-Message-State: APjAAAX+jyN5dFj55ww3InqQXF5NTkygaFTx0+mc2+lx6dRwKnFABpyg Sb0Ck+0c8luu0MHRciA+Huqn3w== X-Google-Smtp-Source: APXvYqxIdhhZ2JdruuDE0wVdfP3W+Q1cj5pKLGr8tiWIFLeuCifPv8CGC4QztbWIeJssrrKzi3Ds7A== X-Received: by 2002:adf:c98f:: with SMTP id f15mr12552255wrh.279.1559462493346; Sun, 02 Jun 2019 01:01:33 -0700 (PDT) Received: from viisi.fritz.box (217-76-161-89.static.highway.a1.net. [217.76.161.89]) by smtp.gmail.com with ESMTPSA id y133sm4868583wmg.5.2019.06.02.01.01.31 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:01:32 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley , Rob Herring , Mark Rutland , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Date: Sun, 2 Jun 2019 01:01:23 -0700 Message-Id: <20190602080126.31075-3-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080126.31075-1-paul.walmsley@sifive.com> References: <20190602080126.31075-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add YAML DT binding documentation for the SiFive FU540 SoC. This SoC is documented at: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216. This second version incorporates review feedback from Rob Herring . Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Albert Ou Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- .../devicetree/bindings/riscv/sifive.yaml | 25 +++++++++++++++++++ MAINTAINERS | 9 +++++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml new file mode 100644 index 000000000000..ce7ca191789e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive SoC-based boards + +maintainers: + - Paul Walmsley + - Palmer Dabbelt + +description: + SiFive SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - sifive,freedom-unleashed-a00 + - const: sifive,fu540-c000 + - const: sifive,fu540 +... diff --git a/MAINTAINERS b/MAINTAINERS index 5cfbea4ce575..8a64051cf5fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14322,6 +14322,15 @@ S: Supported K: sifive N: sifive +SIFIVE FU540 SYSTEM-ON-CHIP +M: Paul Walmsley +M: Palmer Dabbelt +L: linux-riscv@lists.infradead.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git +S: Supported +K: fu540 +N: fu540 + SILEAD TOUCHSCREEN DRIVER M: Hans de Goede L: linux-input@vger.kernel.org From patchwork Sun Jun 2 08:01:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 1108903 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="fYmCWNef"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45GrHh0VRYz9sNm for ; Sun, 2 Jun 2019 18:01:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726713AbfFBIBi (ORCPT ); Sun, 2 Jun 2019 04:01:38 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:32972 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726690AbfFBIBh (ORCPT ); Sun, 2 Jun 2019 04:01:37 -0400 Received: by mail-wm1-f65.google.com with SMTP id v19so9307188wmh.0 for ; Sun, 02 Jun 2019 01:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wvk9LhsSu5lYNJZOdSQrHtIo1oj0PZh/JKcuQJp9vDo=; b=fYmCWNefUSRRfI+osqI+lUhNWaYMBzKi1H2Jgh1J3ytaXzBPfZ8n7PmRXiJHEqNtA2 6QCDU4fzqtjRFadoh4AvW03PgkUoa0c9+1hTl9fBkpSqygTYFEstCkR+i7/Hs78pSYO8 Yhmdx/YVupO8rnYgqvH1tFa9j+vZctT+lguW3Z0C7V+//qG5b9F+j6099KlUupO4nANt 6/ANWZvJOTVtgRtFldXbtSIJWl8agjg3AeRAWW3pOqb1sWKkb9GYnHlwoNosUD6nDtNc gDb3j6hjgt8++KsMN2TnvxtIyN/iCuC5xa30Cixff6Jmvz/s2ZCFCLfM6TrNvCbkALOH lOsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wvk9LhsSu5lYNJZOdSQrHtIo1oj0PZh/JKcuQJp9vDo=; b=AdXybPVE/Kj3gYn3HINC//Ek75nABgQRwV51SHsfdvkFayzkQit6o/BK5Feh7D2QeY zcbrnfzFH62SDSFD+fjW08Yn1b5D6wozoK6F1v8IveFbU+hLK6NztNCxntGvkaOGinFp UKb7vopeC2ftYR8PHXQqwkYI6NFzGdiU27UtrJpr2/LD1DNaIRWQ5gZ+3tcmrHs15fu7 CSFSTMNOGj75M2X3UduHb9FDXYeV8WwWIPrybMVuHyFv26v64E6n/M2qQ+H/K/XrB2Ek gR57BJJ+kOAOpHeXFiPv6THLS1snGhWsq38ccamDQjboZq0UM6FU7PxXEcEPw4udmQTw 5okQ== X-Gm-Message-State: APjAAAUwW1mdnGPRYZ+VFjaNLaLjgWZWMA2qh36jr7cVYPOM4oYHY84k S9H9MPl19v0fW2iGmMf4m2M1k5iJ3Go= X-Google-Smtp-Source: APXvYqzpLgXJz0d8esI7yjy/QZEZ9WVxaBsUd5yMABicDTGu4rF+DDeW58ycRKqcWXSD5LajTSzwBw== X-Received: by 2002:a1c:7314:: with SMTP id d20mr10759521wmb.53.1559462494788; Sun, 02 Jun 2019 01:01:34 -0700 (PDT) Received: from viisi.fritz.box (217-76-161-89.static.highway.a1.net. [217.76.161.89]) by smtp.gmail.com with ESMTPSA id y133sm4868583wmg.5.2019.06.02.01.01.33 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:01:34 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley , Rob Herring , Mark Rutland , Lorenzo Pieralisi , devicetree@vger.kernel.org Subject: [PATCH 3/5] dt-bindings: riscv: convert cpu binding to json-schema Date: Sun, 2 Jun 2019 01:01:24 -0700 Message-Id: <20190602080126.31075-4-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080126.31075-1-paul.walmsley@sifive.com> References: <20190602080126.31075-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At Rob's request, we're starting to migrate our DT binding documentation to json-schema YAML format. Start by converting our cpu binding documentation. While doing so, document more properties and nodes. This includes adding binding documentation support for the E51 and U54 CPU cores ("harts") that are present on this SoC. These cores are described in: https://static.dev.sifive.com/FU540-C000-v1.0.pdf This cpus.yaml file is intended to be a starting point and to evolve over time. It passes dt-doc-validate as of the yaml-bindings commit 4c79d42e9216. This patch was originally based on the ARM json-schema binding documentation as added by commit 672951cbd1b7 ("dt-bindings: arm: Convert cpu binding to json-schema"). Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Lorenzo Pieralisi Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-riscv@lists.infradead.org Reviewed-by: Rob Herring --- .../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml new file mode 100644 index 000000000000..6e8d55d9d4e1 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V bindings for 'cpus' DT nodes + +maintainers: + - Paul Walmsley + - Palmer Dabbelt + +allOf: + - $ref: /schemas/cpus.yaml# + +properties: + $nodename: + const: cpus + description: Container of cpu nodes + + '#address-cells': + const: 1 + description: | + A single unsigned 32-bit integer uniquely identifies each RISC-V + hart in a system. (See the "reg" node under the "cpu" node, + below). + + '#size-cells': + const: 0 + +patternProperties: + '^cpu@[0-9a-f]+$': + properties: + compatible: + type: array + items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + description: + Identifies that the hart uses the RISC-V instruction set + and identifies the type of the hart. + + mmu-type: + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: + - riscv,sv32 + - riscv,sv39 + - riscv,sv48 + description: + Identifies the MMU address translation mode used on this + hart. These values originate from the RISC-V Privileged + Specification document, available from + https://riscv.org/specifications/ + + riscv,isa: + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: + - rv64imac + - rv64imafdc + description: + Identifies the specific RISC-V instruction set architecture + supported by the hart. These are documented in the RISC-V + User-Level ISA document, available from + https://riscv.org/specifications/ + + timebase-frequency: + type: integer + minimum: 1 + description: + Specifies the clock frequency of the system timer in Hz. + This value is common to all harts on a single system image. + + interrupt-controller: + type: object + description: Describes the CPU's local interrupt controller + + properties: + '#interrupt-cells': + const: 1 + + compatible: + const: riscv,cpu-intc + + interrupt-controller: true + + required: + - '#interrupt-cells' + - compatible + - interrupt-controller + + required: + - riscv,isa + - timebase-frequency + - interrupt-controller + +examples: + - | + // Example 1: SiFive Freedom U540G Development Kit + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + cpu_intc0: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu_intc1: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + - | + // Example 2: Spike ISA Simulator with 1 Hart + cpus { + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; +...