From patchwork Fri May 24 00:06:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1104550 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="obUAuUIt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4596Bx4lBKz9s9T for ; Fri, 24 May 2019 10:07:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388684AbfEXAH3 (ORCPT ); Thu, 23 May 2019 20:07:29 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:37265 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388425AbfEXAH2 (ORCPT ); Thu, 23 May 2019 20:07:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558656448; x=1590192448; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GED2GA9QcE13vUl5xR4mTzXTMt8Lm/cPPiiomsp+YVU=; b=obUAuUIt/UT9YONdGj5aAe7nyJ+5ubfBwJmKpk2zgzvAs766jbSfuTdd U7cnqDSFb+lIIeYNtIG4ps690LYLhxbcxct3xIPPbqZxWwvzAptwUfyRf xuPbGLXRMtIeigZxv5w0aioB0zWpZfngmSKVRZwHrUhNmsp4uYWpzxmOM AAkxCm9n3eioKsw3hWjBoBhyGa6cMuGfJ33aa3zAgTOwwzSVu52mhP9OO GJqcTUUAMutt9qKBipVkU3a7eKJOhsVw45L3X3h4g0GlTi3Dk/JJs5ehL Vdpeb4b8cgYwAJvvtv6LK2an2sPMS5vc0T/DMFoo7NHiG4CqfBV5iRSeV Q==; X-IronPort-AV: E=Sophos;i="5.60,505,1549900800"; d="scan'208";a="108976452" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 May 2019 08:07:26 +0800 IronPort-SDR: 7dYyZsuQPTbahR8Po1JuSt2YcSX3mvzPDX7V5YenpeSuXcDH3IcCa6zM/knzcYeFUnj9NwbVvu RVIdJ7iDGh8FVJuzkZ8FFraqHLQ378vChaYfbzcWApQHt0OJ83SA1U15hhKrV+akEX7ekCjjPA Tll/Bk7jXRPkYPRLKfeqdV0UX8hd1OP4lkTXmYYp/vVtFGVLwAzGAgo87zKPENGXAlEhbHluai Lt2U3R7UaAZyNsFdXMCRtelyDI2sP0n7zdhMqkALBTJ56VG3qGBpWJetlbFrhfLgTkQtTHSGMs Sw2irdHsNWs8+g3eEmlqKd1K Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 23 May 2019 16:45:08 -0700 IronPort-SDR: 341jEcSs6pSCjQ27H/KQc3ZHyavI69B6lqsdo28+lkRjZYQlZhRKYL6fFHFnMqSkPyjC2YpFjN zgf5XrjEEjr8QBjGGvG/0WiRgUIkA5iz8PX4gzAfQfnrfLobcPvqyxh88Fr+aWw08EN4duinZA dJFRPpcTHeyc31oDWsGsAXy71D7XdUkLHJjHUOyGTxH2Xh+EsBD7biDVoZpWsOaOoMwVsWGTY/ F3mUzmQiap9ZbpO05xrow58G5i4810s27v9u9q9+PMc7WJdNlSpQNtGGQrPnl/RT9bVMZu4Qdj xyg= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 23 May 2019 17:07:26 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Sudeep Holla , Rob Herring , Albert Ou , Andreas Schwab , Anup Patel , Atish Patra , Catalin Marinas , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , linux-riscv@lists.infradead.org, Mark Rutland , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [RFT PATCH v5 1/5] Documentation: DT: arm: add support for sockets defining package boundaries Date: Thu, 23 May 2019 17:06:48 -0700 Message-Id: <20190524000653.13005-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190524000653.13005-1-atish.patra@wdc.com> References: <20190524000653.13005-1-atish.patra@wdc.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sudeep Holla The current ARM DT topology description provides the operating system with a topological view of the system that is based on leaf nodes representing either cores or threads (in an SMT system) and a hierarchical set of cluster nodes that creates a hierarchical topology view of how those cores and threads are grouped. However this hierarchical representation of clusters does not allow to describe what topology level actually represents the physical package or the socket boundary, which is a key piece of information to be used by an operating system to optimize resource allocation and scheduling. Lets add a new "socket" node type in the cpu-map node to describe the same. Signed-off-by: Sudeep Holla Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/topology.txt | 52 ++++++++++++++----- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt index b0d80c0fb265..3b8febb46dad 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/arm/topology.txt @@ -9,6 +9,7 @@ ARM topology binding description In an ARM system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: +- socket - cluster - core - thread @@ -63,21 +64,23 @@ nodes are listed. The cpu-map node's child nodes can be: - - one or more cluster nodes + - one or more cluster nodes or + - one or more socket nodes in a multi-socket system Any other configuration is considered invalid. -The cpu-map node can only contain three types of child nodes: +The cpu-map node can only contain 4 types of child nodes: +- socket node - cluster node - core node - thread node whose bindings are described in paragraph 3. -The nodes describing the CPU topology (cluster/core/thread) can only -be defined within the cpu-map node and every core/thread in the system -must be defined within the topology. Any other configuration is +The nodes describing the CPU topology (socket/cluster/core/thread) can +only be defined within the cpu-map node and every core/thread in the +system must be defined within the topology. Any other configuration is invalid and therefore must be ignored. =========================================== @@ -85,26 +88,44 @@ invalid and therefore must be ignored. =========================================== cpu-map child nodes must follow a naming convention where the node name -must be "clusterN", "coreN", "threadN" depending on the node type (ie -cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which -are siblings within a single common parent node must be given a unique and +must be "socketN", "clusterN", "coreN", "threadN" depending on the node type +(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes +which are siblings within a single common parent node must be given a unique and sequential N value, starting from 0). cpu-map child nodes which do not share a common parent node can have the same name (ie same number N as other cpu-map child nodes at different device tree levels) since name uniqueness will be guaranteed by the device tree hierarchy. =========================================== -3 - cluster/core/thread node bindings +3 - socket/cluster/core/thread node bindings =========================================== -Bindings for cluster/cpu/thread nodes are defined as follows: +Bindings for socket/cluster/cpu/thread nodes are defined as follows: + +- socket node + + Description: must be declared within a cpu-map node, one node + per physical socket in the system. A system can + contain single or multiple physical socket. + The association of sockets and NUMA nodes is beyond + the scope of this bindings, please refer [2] for + NUMA bindings. + + This node is optional for a single socket system. + + The socket node name must be "socketN" as described in 2.1 above. + A socket node can not be a leaf node. + + A socket node's child nodes must be one or more cluster nodes. + + Any other configuration is considered invalid. - cluster node Description: must be declared within a cpu-map node, one node per cluster. A system can contain several layers of - clustering and cluster nodes can be contained in parent - cluster nodes. + clustering within a single physical socket and cluster + nodes can be contained in parent cluster nodes. The cluster node name must be "clusterN" as described in 2.1 above. A cluster node can not be a leaf node. @@ -164,13 +185,15 @@ Bindings for cluster/cpu/thread nodes are defined as follows: 4 - Example dts =========================================== -Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters): +Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single +physical socket): cpus { #size-cells = <0>; #address-cells = <2>; cpu-map { + socket0 { cluster0 { cluster0 { core0 { @@ -253,6 +276,7 @@ cpus { }; }; }; + }; CPU0: cpu@0 { device_type = "cpu"; @@ -473,3 +497,5 @@ cpus { =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml +[2] Devicetree NUMA binding description + Documentation/devicetree/bindings/numa.txt From patchwork Fri May 24 00:06:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1104549 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="AtSj73YV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4596Bw75Bdz9s6w for ; Fri, 24 May 2019 10:07:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388629AbfEXAH3 (ORCPT ); Thu, 23 May 2019 20:07:29 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:37268 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388681AbfEXAH2 (ORCPT ); Thu, 23 May 2019 20:07:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558656448; x=1590192448; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=29osV+2RDGf1LHK2n5eg5QB1HBqM11BN+lKruv8f5mA=; b=AtSj73YVWkLihbC08N5oqnYIE1geZLNgeHla9D/HPAx2P0hkLH4zDXVM WtRb3BD24g7QsuswnThNs0hFJDYDZc+SsW529pET45Rf8DdrZ5G0YXriC Gnv1DOR5clr/g6b7opXqNlUuxXtyw28mgGO6zFvtIJX4LcpmWe9uENnCE O4UYFiEDAN/GMcqOg365Q+hGVxx6wK0baNkAiUaoUQSKYtD5yFXoL48q/ V7XF2jLHm6EHOjmE0qIcH40FHxRIInjk1LO4FcVNpdqMukiGJNNGHljXF FMP/fyO9/Hfdy8ClslVtmUS1TsxahBYUlhAfV7qeT5f1F7H5Nn/e82yL4 A==; X-IronPort-AV: E=Sophos;i="5.60,505,1549900800"; d="scan'208";a="108976457" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 May 2019 08:07:27 +0800 IronPort-SDR: 0MBqP4HVsddNg4VRh93Y4uFWlIJWsoDbLklWrag6dFq2rZzUI2h2MMkxEi8e2fYdeVDhmO3C+C Ta5EKSjwnMP4JoY0siLmRzXXj9D15OnbJadcZSDnMGYPFfw4vmajo9dHt7F9B7HmCcLvPM79Mu WU7aU09j9DdrEYVixK8e7S0NKKaYwHWOmpRaCa653kF5iX231hz0UrnB+du75nVlyView292O+ BJnHGrw46WK7w91YhQQzSybiU/mtFl1mu2U4CCrA3rLa4dFEpWWTF9lMemLwWy5tHHP6hgau1W uF7DCXG6m7iAGSjnrkmifF2q Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 23 May 2019 16:45:08 -0700 IronPort-SDR: sGoOb3SBVWPqEzlp/cOI6PnfGoxO910h/k2WIqdFLLXGR1nEjMv7fYSdJlzcFZaB62zMWdrEjp uuTGxWBeZenLjzUULhUvHjJRarDaTOWMmZvzl/ubUGSC529i0SWX9+N9QJ/lTPUtiYDxx4jjgG bek3lD1BYfx0/JJf6W4Sj26O6J6t89yQqzKL5rVIeMoPB+VyiVhpOv0jmx4Hq6fiXJ3BdU2nx9 V4uR1gKcnQFRMQ/H21wysK+IZywP0NIQOW+c7ZotTeAlKxyscMs2txd/S1KiBkbv8uEiRujE8O dvs= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 23 May 2019 17:07:26 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Sudeep Holla , Rob Herring , Albert Ou , Andreas Schwab , Anup Patel , Catalin Marinas , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , linux-riscv@lists.infradead.org, Mark Rutland , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [RFT PATCH v5 2/5] dt-binding: cpu-topology: Move cpu-map to a common binding. Date: Thu, 23 May 2019 17:06:49 -0700 Message-Id: <20190524000653.13005-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190524000653.13005-1-atish.patra@wdc.com> References: <20190524000653.13005-1-atish.patra@wdc.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra Reviewed-by: Sudeep Holla Reviewed-by: Rob Herring --- .../topology.txt => cpu/cpu-topology.txt} | 82 +++++++++++++++---- 1 file changed, 66 insertions(+), 16 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt similarity index 86% rename from Documentation/devicetree/bindings/arm/topology.txt rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt index 3b8febb46dad..069addccab14 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt @@ -1,12 +1,12 @@ =========================================== -ARM topology binding description +CPU topology binding description =========================================== =========================================== 1 - Introduction =========================================== -In an ARM system, the hierarchy of CPUs is defined through three entities that +In a SMP system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: - socket @@ -14,9 +14,6 @@ are used to describe the layout of physical CPUs in the system: - core - thread -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - The bottom hierarchy level sits at core or thread level depending on whether symmetric multi-threading (SMT) is supported or not. @@ -25,33 +22,31 @@ threads existing in the system and map to the hierarchy level "thread" above. In systems where SMT is not supported "cpu" nodes represent all cores present in the system and map to the hierarchy level "core" above. -ARM topology bindings allow one to associate cpu nodes with hierarchical groups +CPU topology bindings allow one to associate cpu nodes with hierarchical groups corresponding to the system hierarchy; syntactically they are defined as device tree nodes. -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: +Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be +used for any other architecture as well. -https://www.devicetree.org/specifications/ +The cpu nodes, as per bindings defined in [4], represent the devices that +correspond to physical CPUs and are to be mapped to the hierarchy levels. -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. +with bindings standardized in [4] is therefore considered invalid. =========================================== 2 - cpu-map node =========================================== -The ARM CPU topology is defined within the cpu-map node, which is a direct +The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct child of the cpus node and provides a container where the actual topology nodes are listed. - cpu-map node - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology + Usage: Optional - On SMP systems provide CPUs topology to the OS. + Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. @@ -494,8 +489,63 @@ cpus { }; }; +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) + +{ + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + ... + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU1>; + }; + core1 { + cpu = <&CPU2>; + }; + core2 { + cpu0 = <&CPU2>; + }; + core3 { + cpu0 = <&CPU3>; + }; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x1>; + } + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x2>; + } + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x3>; + } + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x4>; + } + } +}; =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml [2] Devicetree NUMA binding description Documentation/devicetree/bindings/numa.txt +[3] RISC-V Linux kernel documentation + Documentation/devicetree/bindings/riscv/cpus.txt +[4] https://www.devicetree.org/specifications/