From patchwork Sun May 12 17:46:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1098565 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FNPLCR8S"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 452BGZ6Kr4z9sPS for ; Mon, 13 May 2019 03:47:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726934AbfELRqT (ORCPT ); Sun, 12 May 2019 13:46:19 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:34520 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726605AbfELRqS (ORCPT ); Sun, 12 May 2019 13:46:18 -0400 Received: by mail-wm1-f66.google.com with SMTP id m20so9712326wmg.1; Sun, 12 May 2019 10:46:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=FNPLCR8Sd13vMzZbJg8ptcgHXtjdN1eS0ZvAd0uRFvifNg+n8JpiAcG8DD3rDOsdu3 xiheRxeCsEA5ATtOgkuuqVXHPzZJGNRMRUdPHZ1jIQu/yLNphwgNpLNI3gBGMVHQDVZv P2ULCWwuKNIltsEqQWfvKPwwloxjdzfVnyekrJRLrh2wmTakO94vwauG5Os4o1iPEvHj Q3cMxNcOEmPQWVeqM8CxPFspXuvki4g0PULvuebwMYm8rmtBFRCGGjHrEzuHtLdGv2Fb 5rhSafvgxQVouj4xJmdbx7IWn9lKFcY132hkVU6fW8iQcEfdAcTkpYXh5GP01eC4SQtu Uzig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=cr7WarBE0XUQn45eK53mG/FbgQ0XKLYs8ofz8p9493+mKah3RL3dleGQdggWzoIIlb NyOSlPx41QvhXdgepHr2ThlsXPCAwpoEquyIJJ1hETad5TGy4M76JvGT5FeFDeCXcFUZ w8it2FX/iV+bVrZ/pXYkfZmrezYQqCvVNnqtaI5EyfFAmLrm+pdWYM69DoWvxkJBq/Fp E8AqlgOGB0juszUJ6i8NvTIMswSTNQp5zHxID1pNX3O58TzaQcRV/yIwjbz0FNRfZHXe 1rmd75ieMo2EfgpZ4qK6wPnuP36ic+IA0dmFW9vb+J+/PMCn4Kvf72Qc0YoBmMHAGlpe 6XDg== X-Gm-Message-State: APjAAAXecRZm9BDTJRXEaSLF66s6rVrapUjbwGBfIxy3nJ/Pxyy6Dbnr xAVKigN8llQESwP10QETaKA= X-Google-Smtp-Source: APXvYqx2EWKBm+GH/a0JjB7RxHj0gE/6taBHkxJHevcGOh44GOKAT3CUGk1nxZQ0yStWTZtn7JbA/w== X-Received: by 2002:a1c:a684:: with SMTP id p126mr8448133wme.101.1557683176596; Sun, 12 May 2019 10:46:16 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id d14sm9090558wre.78.2019.05.12.10.46.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 May 2019 10:46:15 -0700 (PDT) From: peron.clem@gmail.com To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Neil Armstrong , Kevin Hilman Subject: [PATCH v4 1/8] dt-bindings: gpu: mali-midgard: Add resets property Date: Sun, 12 May 2019 19:46:01 +0200 Message-Id: <20190512174608.10083-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190512174608.10083-1-peron.clem@gmail.com> References: <20190512174608.10083-1-peron.clem@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Neil Armstrong The Amlogic ARM Mali Midgard requires reset controls to power on and software reset the GPU, adds these as optional in the bindings. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..1b1a74129141 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -37,6 +37,20 @@ Optional properties: - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt for details. +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-gxm-mali" + Required properties: + - resets : Should contain phandles of : + + GPU reset line + + GPU APB glue reset line Example for a Mali-T760: From patchwork Sun May 12 17:46:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1098564 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AjsEnXYi"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 452BGZ2P4fz9sPR for ; Mon, 13 May 2019 03:47:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726605AbfELRq4 (ORCPT ); Sun, 12 May 2019 13:46:56 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:44851 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726529AbfELRqU (ORCPT ); Sun, 12 May 2019 13:46:20 -0400 Received: by mail-wr1-f67.google.com with SMTP id c5so12680312wrs.11; Sun, 12 May 2019 10:46:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2w/o0YvWj4GW2dKc8xosf8L/TwKxnX3w/M6Sh7NSyHk=; b=AjsEnXYimdr8AvydteCtPqKKl4nVXnBE3i0ABKHq/uJCZi98gqAOEJgPbS7s5lnb7d 8AbtSEb/imSgq1c4/AUmc6O/cboc0TJGeCLfOp5Z3oNlvT9V9iVXZXEKeQQMhr8t1lRM YaT2dlb4MSUgf73LLkrdJA19XRmXH41HYOryaYBusMPZZdr04tXBk2k3TPhwIrTwIFL+ F1JPK6mLy6Fqvl3p0WlAv5jCn2oIU6MEJ3efLRpIq7BrqCaE3nXnVTIKTnt9g9h7kU0W 9SxtSgkGYN+D7UvI0CpXOQ3IbHf0wsrlQtgOHOeCESbKGDvOgP49Z67LcO6RGwEXR3uA ziQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2w/o0YvWj4GW2dKc8xosf8L/TwKxnX3w/M6Sh7NSyHk=; b=FDqKn3ZJ+lVYe0txxgyqkkRA8u1cTYoI9+jE892VLAVOGQi5ngBa2M3VKbPMt0s34D wi+LzqNxUAKZJsGRtmG1vsOFIg7lfu5mp28AiOl7oSTk8hHnKYEC9dKUYfK+TssWLOfh k9qUrt/QJfTdZapUyZmGn5lLdHvMMGkVMXTyy/G2ffZQXxIE01xNnThLI5h2VqC637/+ GF9xj1JTFfh2OMBgfrslrJFRTt0L8e7elD1HPj5IR1Ac9+Qeh7jvkwWTXEXHKUMZliii PXt/RhMz1+b0BhUki0ZjVsEj8VcQ8+w31uUtho8JWMnLqc+HX7Bw5LlzqZvUSEBOmkBx mrhA== X-Gm-Message-State: APjAAAXo66GbhwSWyxOCHa4uIlow4wHJpQB8JU1zQi6C9MaoH3ZJanS3 Itpxr9hJeYr2lfTxQ+/GyRg= X-Google-Smtp-Source: APXvYqzvp8ezt6AmI9jIyt2T+HF6x4fAV9SfcMVOJ7+O+OXtpp/dMmSAZ2wvp2VfVb1lYQz+lHV//w== X-Received: by 2002:a5d:4fd2:: with SMTP id h18mr15357356wrw.117.1557683177903; Sun, 12 May 2019 10:46:17 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id d14sm9090558wre.78.2019.05.12.10.46.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 May 2019 10:46:16 -0700 (PDT) From: peron.clem@gmail.com To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Icenowy Zheng , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 2/8] dt-bindings: gpu: add bus clock for Mali Midgard GPUs Date: Sun, 12 May 2019 19:46:02 +0200 Message-Id: <20190512174608.10083-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190512174608.10083-1-peron.clem@gmail.com> References: <20190512174608.10083-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Icenowy Zheng Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. + * core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) + * bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. From patchwork Sun May 12 17:46:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1098563 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C87Q+0KZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 452BGD2zx8z9sPV for ; Mon, 13 May 2019 03:46:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726979AbfELRqX (ORCPT ); Sun, 12 May 2019 13:46:23 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:50660 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726946AbfELRqV (ORCPT ); Sun, 12 May 2019 13:46:21 -0400 Received: by mail-wm1-f68.google.com with SMTP id f204so6170820wme.0; Sun, 12 May 2019 10:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EXpuW1H5E6JQJvkk+bffS60LiMlJ6FTGBpL+lRXA+/0=; b=C87Q+0KZQadrQrFy/za95yC+j5F9HIcOk+MD/C9HIXG+ocEQapjM4S2ITPa0BLHET0 TveZfiYQ/0GIB0Q3RDpOCPvI8Dq5yBr0wNvFMerC0oF3tyITvUzD/EMkVuawaWcZUeJW Losyzn7J5obpJCtjMEmo4hNYOj5ULqh8Mdo7ZOuLLhrEEMff8cwte3uzAy4fMbRvy94O YdhlCq/6M2Vyhu/IoB60ud/+9jDueB89Y3+rz/lRGzS5vw/O/YtZa+uLqVQsxXQ+yUt3 yyK0Fznt12O+GzSnJ+cMNNwKLT0DYr5HX1QPF3OWWx5m5t/RszjCKfW0+mrczm8pWipQ Jn0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EXpuW1H5E6JQJvkk+bffS60LiMlJ6FTGBpL+lRXA+/0=; b=U0627i1f9p5dEa0I6BThK6v2LOqhGPOYLJpwiCEhmiV/9QAguQP1SKJaM4ui/VXFs/ 6YhiEBLz/MaNFg0Ym848QeHn8XE62Jn6xBp3TmASgo8c0ctQucl+DhLxGIZFBrmJ4w/z PewbxFKv4rIcktzszUzfWYJIvSS1CsfA7E4UX9PMeOlMDaCHNz/3cNJoShlJiqvfkKaD cftinl8TmMlFFGTkZ+auVCi2eIfPqUgwNU5qTMyR22btMfzX+/os12unrD0qRF1VNCcF LtdvVHRAMkNVgKFiSFKRM1pWsqp9gKux1bjequFIEe+UuiK1jgInsWmk4JyJG9ULVywV tqmA== X-Gm-Message-State: APjAAAXjx6duR90unSDvJskPrk5GYbJo6+WMFojf7jdJH5+IN65aeW2h Dk+H+URQuzjySrFcmCWvwDo= X-Google-Smtp-Source: APXvYqxhB7vibCkxRA4FPfP8y01EU8vmUJIZfLKUu16/cqguHPZ7Vjvf/kWOGAn7GjdIKhCBtdMUHg== X-Received: by 2002:a1c:7a12:: with SMTP id v18mr13528180wmc.69.1557683179040; Sun, 12 May 2019 10:46:19 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id d14sm9090558wre.78.2019.05.12.10.46.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 May 2019 10:46:18 -0700 (PDT) From: peron.clem@gmail.com To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 3/8] dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible Date: Sun, 12 May 2019 19:46:03 +0200 Message-Id: <20190512174608.10083-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190512174608.10083-1-peron.clem@gmail.com> References: <20190512174608.10083-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Clément Péron This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..4bf17e1cf555 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: + + "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,15 @@ Vendor-specific bindings ------------------------ The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - clocks : phandles to core and bus clocks + - clock-names : must contain "core" and "bus" + - resets: phandle to GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of :