From patchwork Thu May 9 18:08:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1097628 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HCoempkf"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 450Lvm3qjrz9s9y for ; Fri, 10 May 2019 04:09:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2A980C21DFB; Thu, 9 May 2019 18:08:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 788E0C21C8B; Thu, 9 May 2019 18:08:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E61FC21BE5; Thu, 9 May 2019 18:08:19 +0000 (UTC) Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by lists.denx.de (Postfix) with ESMTPS id A8AC8C21BE5 for ; Thu, 9 May 2019 18:08:19 +0000 (UTC) Received: by mail-wr1-f68.google.com with SMTP id l2so4281309wrb.9 for ; Thu, 09 May 2019 11:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vK74zrKxUghzyAKwVP2HbVAdzGMmHic4g/O8Vk09s8E=; b=HCoempkfO4C4MGPYcPilsE7SkNK9c58orK50KMBPbFcFTBHHl9bmXdJh5BAhLgqh3e 3UxPfkkU5gNPIOnlUwuGrA1TRcFkUmo18Ll7tOeEofg4lbGMfvNWCYjWtyX4INerwcee +e2klHKKM2Hk474rKCk3C0RTLBdaokdXnW5P+El8gZmOsZqtUOMNSAz9OSZST81BrwfK hcaQeOiVDeobdHMnRas07ZLPP54/0BPYc38IskKtL88Ef5AAQa/U8g8XtfVpBpmnd9JW ugFtYbFZ/skmTFXdbNNN5OVNtMlYw560YhqEonGSQMAII4Dr9r1wZcpMrGv8kvjndBEf HkqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vK74zrKxUghzyAKwVP2HbVAdzGMmHic4g/O8Vk09s8E=; b=C4MtIx/Ea1cgF1qNCRzSHJxXPfzG1iW5xTBy47YIs5cyK1I2ovYGF3jIv2849KNcsf Ay/oA9vPoaYHOSkUL4T6k39MnNOsk+gc3FT6OrIFkzQpCZ6pfL/NT5+yctMY/Iom7OFP NXFOJ+CY95j3nRNCmzg1Cd/J4uWToiJuqy963EFjCczhhZ3LJj/fwFFnaPPj5u9WHXEO DVD39il8J0KTFL2DbZXKr5nGrko9dfDV6zSbHNTJ61dbJj/+F0Yg4DaANPyZBwh5QkKE apfxDCiGe/rRPIoLnxQmDYH10v4x9aM+ndlEydJOKcGc+yLtKiST+ERgOoCSVhQBKufa 9Cxg== X-Gm-Message-State: APjAAAVxvjAW8KDvlaa1JhZvbgLamGhHKAvbV43h2xKnv+2VC7i870Mb vXLTHcpPCEgBcWb1c9K4XcBODWIr X-Google-Smtp-Source: APXvYqznvfpex9YEwLbkjLVws3ZUmPdcL1t6XbtLZdrMNZuS8/pj07Jv8ytNq3v18560JKk9v5yzRw== X-Received: by 2002:a5d:4e8d:: with SMTP id e13mr1460546wru.299.1557425298120; Thu, 09 May 2019 11:08:18 -0700 (PDT) Received: from ubuntu.home ([2a02:8071:6a3:700:2df8:99ba:e50f:756b]) by smtp.gmail.com with ESMTPSA id j1sm2765329wrt.52.2019.05.09.11.08.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 11:08:16 -0700 (PDT) From: Simon Goldschmidt To: u-boot@lists.denx.de, Marek Vasut Date: Thu, 9 May 2019 20:08:04 +0200 Message-Id: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Cc: Chin Liang See , Tom Rini Subject: [U-Boot] [PATCH v3 1/4] arm: socfpga: rst: add register definition for cold reset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a define for the bit in rstmgr's ctrl regiser that issues a cold reset (we had a define for the warm reset bit only) in preparation for a proper sysrese driver. Signed-off-by: Simon Goldschmidt Series changes: 2 - separate this patch to the register descriptions from the actual sysreset driver patch --- Changes in v3: None Changes in v2: None arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 42beaecdd6..6ad037e325 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -11,6 +11,7 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 /* From patchwork Thu May 9 18:08:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1097626 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 09 May 2019 11:08:18 -0700 (PDT) From: Simon Goldschmidt To: u-boot@lists.denx.de, Marek Vasut Date: Thu, 9 May 2019 20:08:05 +0200 Message-Id: <20190509180807.30142-2-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> References: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> MIME-Version: 1.0 Cc: Michal Simek Subject: [U-Boot] [PATCH v3 2/4] sysreset: socfpga: gen5: add sysreset driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5. Signed-off-by: Simon Goldschmidt --- Changes in v3: - moved socfpga gen5 sysreset driver to extra patch Changes in v2: None drivers/sysreset/Kconfig | 7 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga.c | 56 +++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 drivers/sysreset/sysreset_socfpga.c diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 8ce3e2e207..066838c106 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -36,6 +36,13 @@ config SYSRESET_PSCI Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. +config SYSRESET_SOCFPGA + bool "Enable support for Intel SOCFPGA family" + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + help + This enables the system reset driver support for Intel SOCFPGA SoCs + (Cyclone 5, Arria 5 and Arria 10). + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index b3728ac17f..0241b0132d 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o +obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c new file mode 100644 index 0000000000..fc1ba72d5b --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt + */ + +#include +#include +#include +#include +#include +#include + +struct socfpga_sysreset_data { + struct socfpga_reset_manager *rstmgr_base; +}; + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + struct socfpga_sysreset_data *data = dev_get_priv(dev); + + switch (type) { + case SYSRESET_WARM: + writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, + &data->rstmgr_base->ctrl); + break; + case SYSRESET_COLD: + writel(1 << RSTMGR_CTRL_SWCOLDRSTREQ_LSB, + &data->rstmgr_base->ctrl); + break; + default: + return -EPROTONOSUPPORT; + } + return -EINPROGRESS; +} + +static int socfpga_sysreset_probe(struct udevice *dev) +{ + struct socfpga_sysreset_data *data = dev_get_priv(dev); + + data->rstmgr_base = devfdt_get_addr_ptr(dev); + return 0; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data), + .ops = &socfpga_sysreset, + .probe = socfpga_sysreset_probe, +}; From patchwork Thu May 9 18:08:06 2019 Content-Type: text/plain; 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Thu, 09 May 2019 11:08:19 -0700 (PDT) From: Simon Goldschmidt To: u-boot@lists.denx.de, Marek Vasut Date: Thu, 9 May 2019 20:08:06 +0200 Message-Id: <20190509180807.30142-3-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> References: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> MIME-Version: 1.0 Cc: Michal Simek Subject: [U-Boot] [PATCH v3 3/4] sysreset: socfpga: stratix10: add sysreset driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10. Signed-off-by: Simon Goldschmidt --- Changes in v3: - moved socfpga stratix sysreset driver to extra patch Changes in v2: None drivers/sysreset/Kconfig | 7 ++++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_s10.c | 29 +++++++++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 drivers/sysreset/sysreset_socfpga_s10.c diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 066838c106..5b8402ccae 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -43,6 +43,13 @@ config SYSRESET_SOCFPGA This enables the system reset driver support for Intel SOCFPGA SoCs (Cyclone 5, Arria 5 and Arria 10). +config SYSRESET_SOCFPGA_S10 + bool "Enable support for Intel SOCFPGA Stratix 10" + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + help + This enables the system reset driver support for Intel SOCFPGA + Stratix SoCs. + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 0241b0132d..71291fa2cf 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o +obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga_s10.c b/drivers/sysreset/sysreset_socfpga_s10.c new file mode 100644 index 0000000000..9837aadf64 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_s10.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt + */ + +#include +#include +#include +#include +#include + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +}; From patchwork Thu May 9 18:08:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1097629 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rycUwF/9"; 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Thu, 09 May 2019 11:08:21 -0700 (PDT) Received: from ubuntu.home ([2a02:8071:6a3:700:2df8:99ba:e50f:756b]) by smtp.gmail.com with ESMTPSA id j1sm2765329wrt.52.2019.05.09.11.08.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 11:08:20 -0700 (PDT) From: Simon Goldschmidt To: u-boot@lists.denx.de, Marek Vasut Date: Thu, 9 May 2019 20:08:07 +0200 Message-Id: <20190509180807.30142-4-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> References: <20190509180807.30142-1-simon.k.r.goldschmidt@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v3 4/4] sysreset: add support for socfpga sysreset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga to a UCLASS_SYSRESET based dm driver. A side effect is that gen5 and a10 can now select between cold and warm reset. Signed-off-by: Simon Goldschmidt --- Changes in v3: - this patch enables the new drivers and drops the ad-hoc code Changes in v2: - adapt to patch that separates drivers/sysreset from drivers/misc for SPL: select SPL_SYSRESET_SUPPORT, not SPL_DRIVERS_MISC_SUPPORT - separate gen5/a10 driver from s10 driver - as sysreset is a function of rstmgr, bind the sysreset drivers from rstmgr to get the base address instead of hardcoding it arch/arm/Kconfig | 4 +++ arch/arm/mach-socfpga/Makefile | 1 - arch/arm/mach-socfpga/reset_manager.c | 41 --------------------------- drivers/reset/reset-socfpga.c | 19 +++++++++++++ 4 files changed, 23 insertions(+), 42 deletions(-) delete mode 100644 arch/arm/mach-socfpga/reset_manager.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f91c590f6d..327adbbf0a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -829,10 +829,14 @@ config ARCH_SOCFPGA select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 select SPL_SERIAL_SUPPORT + select SPL_SYSRESET_SUPPORT select SPL_WATCHDOG_SUPPORT select SUPPORT_SPL select SYS_NS16550 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYSRESET + select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e66720447f..fc1181cb27 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,7 +8,6 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o -obj-y += reset_manager.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c deleted file mode 100644 index e0a01ed07a..0000000000 --- a/arch/arm/mach-socfpga/reset_manager.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation - */ - - -#include -#include -#include - -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; -#endif - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); -#else - writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, - &reset_manager_base->ctrl); -#endif - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index cb8312619f..f49f064574 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -132,6 +133,23 @@ static int socfpga_reset_remove(struct udevice *dev) return 0; } +static int socfpga_reset_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + + /* + * The sysreset driver does not have a device node, so bind it here. + * Bind it to the node, too, so that it can get its base address. + */ + ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset", + dev->node, &sys_child); + if (ret) + debug("Warning: No sysreset driver: ret=%d\n", ret); + + return 0; +} + static const struct udevice_id socfpga_reset_match[] = { { .compatible = "altr,rst-mgr" }, { /* sentinel */ }, @@ -141,6 +159,7 @@ U_BOOT_DRIVER(socfpga_reset) = { .name = "socfpga-reset", .id = UCLASS_RESET, .of_match = socfpga_reset_match, + .bind = socfpga_reset_bind, .probe = socfpga_reset_probe, .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops,