From patchwork Sat Apr 27 00:47:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 1091846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-499775-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=temperror (0-bit key) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Y+X70NK+"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="U7ilW9lM"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44rXMr667Lz9s3Z for ; Sat, 27 Apr 2019 10:48:02 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=nY0KliSa2wZS U4IcFIf5CRgpIZAHhNd/IdGCoPXu3p/eBA1hmJ2UmA2nbIsuYLGR31HrTFkrgVlK njxAkPq6NCUv1YEYTkmD3+fnVbSxwv4PO++4Pac6FORt9UnsOFE+7aje1pnzialj eXspkkIn8fnxadnKuruED8l0/VQmy7U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=yzln8uko2TgNarcv29 Z8Cl50x9M=; b=Y+X70NK+uK+cTMUf+T7s7Sztkv+WARH1SjrN/rGygc8dGgaIUM kYazgOtVMGmPcJ8+de/AUpo/6qL/L96OVk5ok/ivTwoZNM8O2cX/G5S+cCK50MKf A9ogYOW1H5dvDOQxzg1loQ1Bs2eiQ9hanfXBHb7DqxFDdajsKxf80mmBQ= Received: (qmail 347 invoked by alias); 27 Apr 2019 00:47:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 334 invoked by uid 89); 27 Apr 2019 00:47:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-21.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=12787, gen_rtx_fmt_ee, sk:can_cre, ashift X-HELO: mail-pl1-f195.google.com Received: from mail-pl1-f195.google.com (HELO mail-pl1-f195.google.com) (209.85.214.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 27 Apr 2019 00:47:52 +0000 Received: by mail-pl1-f195.google.com with SMTP id d5so1724255plr.1 for ; Fri, 26 Apr 2019 17:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=ZVWegQvN5lRafoAikEzL5rtTzNBiDq8hyg2prLXbtAY=; b=U7ilW9lMsErIscOWT8l3OcScXGvQ2BhBivq5PmvwVgWJleNafoLpxGE7QtjI6XsFbt 9Hn5xTblr2XMVfy+v3JSXzQUwLB6keKg5wxFyI4UULjakHF9uQJufKn1cX/VdVkqJeXY Lj9EP/BvfA0QKSfBy6ccPAV9PDSGns/OK0abso0v/VzTQbzMB+QaAoq7XuWEc7spfrqt 25RqO7HgLkzaQZPGauByD/xk/9qdvoI6EcGrCLzXZ2/m50o9+sbx+2Ey0YyJ1SEQI6oM ru8J9+Fex6SG6Q6ubkyIbhgn6UBCsTVuXFxEfIrpa5893hNceFh3cUVfYfnH+etmUW5F q0Fg== Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id h189sm47419969pfc.125.2019.04.26.17.47.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 17:47:50 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Promode modes of constant loads for store insns. Date: Fri, 26 Apr 2019 17:47:47 -0700 Message-Id: <20190427004747.20369-1-jimw@sifive.com> X-IsSubscribed: yes This improves optimization of code storing constants to memory. Given this testcase: void sub1 (int *a, long long *b) { *a = 1; *b = 1; } an unpatched rv64 compiler emits two li instructions, one for an SImode pseudo and one for a DImode pseudo. With the patch, we get a single DImode li insn. This fixes the problem by promoting modes when we need to load a constant that isn't valid as a src for a store instruction into a pseudo. There is some special handling for HImode stores which is preserved by passing the original mode through. This avoids a regression for testcases using HImode stores. There is a testcase added that shows the benefits of the optimization and catches the cases that regressed with earlier versions of the patch. This was tested with cross 32-bit/elf and 64-bit/linux builds and tests. There were no regressions. The new testcase fails without the patch and works with the patch. This was also tested by looking at libc and libstdc++ code sizes. This gives smaller code except in a few cases where moving an instruction out of a loop required an extra prologue/epilogue store/load pair. Committed. Jim gcc/ * config/riscv/riscv-protos.h (riscv_move_integer): Add machine_mode parameter. * config/riscv/riscv.c (riscv_move_integer): New parameter orig_mode. Pass orig_mode to riscv_build_integer. (riscv_split_integer): Pass mode to riscv_move_integer. (riscv_legitimize_const_move): Likewise. (riscv_legitimize_move): For MEM dest and CONST_INT src case, new local promoted_mode. Replace force_reg call with code to load constant into promoted reg and then subreg it for the store. * config/riscv/riscv.md (low+1): Pass mode to riscv_move_integer. gcc/testsuite/ * gcc.target/riscv/load-immediate.c: New. --- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv.c | 42 +++++++++++++++---- gcc/config/riscv/riscv.md | 3 +- .../gcc.target/riscv/load-immediate.c | 32 ++++++++++++++ 4 files changed, 70 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/load-immediate.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 8b510f87df8..5c1002bbc29 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -47,7 +47,7 @@ extern rtx riscv_emit_move (rtx, rtx); extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); extern bool riscv_split_symbol_type (enum riscv_symbol_type); extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); -extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT); +extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); extern bool riscv_legitimize_move (machine_mode, rtx, rtx); extern rtx riscv_subword (rtx, bool); extern bool riscv_split_64bit_move_p (rtx, rtx); diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index e7440f39095..6fb6c6ad372 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -508,8 +508,8 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); - riscv_move_integer (hi, hi, hival); - riscv_move_integer (lo, lo, loval); + riscv_move_integer (hi, hi, hival, mode); + riscv_move_integer (lo, lo, loval, mode); hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); hi = force_reg (mode, hi); @@ -1334,10 +1334,12 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, return x; } -/* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */ +/* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE + is the original src mode before promotion. */ void -riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) +riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, + machine_mode orig_mode) { struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; machine_mode mode; @@ -1345,7 +1347,9 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) rtx x; mode = GET_MODE (dest); - num_ops = riscv_build_integer (codes, value, mode); + /* We use the original mode for the riscv_build_integer call, because HImode + values are given special treatment. */ + num_ops = riscv_build_integer (codes, value, orig_mode); if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */ && num_ops >= riscv_split_integer_cost (value)) @@ -1381,7 +1385,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) /* Split moves of big integers into smaller pieces. */ if (splittable_const_int_operand (src, mode)) { - riscv_move_integer (dest, dest, INTVAL (src)); + riscv_move_integer (dest, dest, INTVAL (src), mode); return; } @@ -1428,7 +1432,31 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) { if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) { - riscv_emit_move (dest, force_reg (mode, src)); + rtx reg; + + if (GET_CODE (src) == CONST_INT) + { + /* Apply the equivalent of PROMOTE_MODE here for constants to + improve cse. */ + machine_mode promoted_mode = mode; + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) < UNITS_PER_WORD) + promoted_mode = word_mode; + + if (splittable_const_int_operand (src, mode)) + { + reg = gen_reg_rtx (promoted_mode); + riscv_move_integer (reg, reg, INTVAL (src), mode); + } + else + reg = force_reg (promoted_mode, src); + + if (promoted_mode != mode) + reg = gen_lowpart (mode, reg); + } + else + reg = force_reg (mode, src); + riscv_emit_move (dest, reg); return true; } diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e3799a5bdd8..fc81daa43ef 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1278,7 +1278,8 @@ "" [(const_int 0)] { - riscv_move_integer (operands[2], operands[0], INTVAL (operands[1])); + riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), + mode); DONE; }) diff --git a/gcc/testsuite/gcc.target/riscv/load-immediate.c b/gcc/testsuite/gcc.target/riscv/load-immediate.c new file mode 100644 index 00000000000..f8fe7473c31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/load-immediate.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */ + +/* Check that we don't have unnecessary load immediate instructions. */ +void +sub1 (int *a, long long *b) +{ + *a = 1; + *b = 1; +} + +void +sub2 (short *a, short *b) +{ + *a = -32768; + *b = 32767; +} + +void +sub3 (int *a, long long *b) +{ + *a = 10000; + *b = 10000; +} + +void +sub4 (int *a, short *b) +{ + *a = 1; + *b = 1; +} +/* { dg-final { scan-assembler-times "\tli\t" 4 } } */