From patchwork Wed Apr 17 17:30:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1087068 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Aj5WOKqF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44kq5h1T49z9s8m for ; Thu, 18 Apr 2019 03:31:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732762AbfDQRaX (ORCPT ); Wed, 17 Apr 2019 13:30:23 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:40649 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729641AbfDQRaW (ORCPT ); Wed, 17 Apr 2019 13:30:22 -0400 Received: by mail-wr1-f65.google.com with SMTP id h4so33023154wre.7; Wed, 17 Apr 2019 10:30:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=Aj5WOKqF+mSgsjBpWaUeAq+PoNX7zsm2Qhnv00UOVUzIGHv1lshy+IKTXP7Ds7rvCG b8bamc97MPZYshmWApE7ZV4d3pL/JHGQX6Np8pW1gMJXk5FL5uJ4b331fWKXHDNims4V +C7s+9KsDih/C0gAo732PAL9htI9biOlbpXT6qQk+ztwuEI8ldXtWb53WS8K+AZe2+DO W/HKBFSRLxC73Fpg3alKPdk2r0TlLoEhPRc0ubdGwOOnCSturulw79N4xX0RYDP7RC5Z ryA32XxdX8A3bHO+XaEw58jJSQK6+Sq+bfhZwr6bwTnvhtOFoMuvMPF4hkGnn6u5mWtp 39GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=q9mL2HVh6rFNsj39EM1ltmHy4QukqChx5EMP3c0UVZ58v9yy0h5guLTnUBIjeie/Vo 9Gv8smaZl0z/NWwcifr+lFM/G7s+pfAmag396EO7ylGLgG2K+Db07Vyelbs2D0Wyt2TP iDbn8wVeX6JyVeCtgUQA4SWcaJUpD47I5avTFO3DYZz/KrtFgcEgYZExuAvPVXkUgHBU 0lwNNETvKTTYKB+DDLB9mEFNkWWUxXzSP4L8JGAnVhMOgQlH7ahwvqG1DSZphhbH2pur NJcowxSFRdHizqvaDDhFyZPUovk2bEmvG4nd1jzqPpbRIJZOIwdkN2QLdppFako0pvTk Rc5Q== X-Gm-Message-State: APjAAAWFIDcu64g9Xky+GVZ//lP7ZIAdduiBvIvgnKMdRrNLFyjIwq3P dqVecYWL/9PSsCLpiW/inDg= X-Google-Smtp-Source: APXvYqwNLMHTqK/0VWA3BJtBaMVwTn+td1BwYu3foSWz0sVgnvDFN9iuDARntEHkupvbB4rlOB+tFA== X-Received: by 2002:adf:b458:: with SMTP id v24mr57683336wrd.46.1555522219879; Wed, 17 Apr 2019 10:30:19 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id c6sm2669306wmb.21.2019.04.17.10.30.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 10:30:17 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Neil Armstrong , Kevin Hilman Subject: [PATCH v3 1/8] dt-bindings: gpu: mali-midgard: Add resets property Date: Wed, 17 Apr 2019 19:30:24 +0200 Message-Id: <20190417173031.9920-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190417173031.9920-1-peron.clem@gmail.com> References: <20190417173031.9920-1-peron.clem@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Neil Armstrong The Amlogic ARM Mali Midgard requires reset controls to power on and software reset the GPU, adds these as optional in the bindings. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..1b1a74129141 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -37,6 +37,20 @@ Optional properties: - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt for details. +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-gxm-mali" + Required properties: + - resets : Should contain phandles of : + + GPU reset line + + GPU APB glue reset line Example for a Mali-T760: From patchwork Wed Apr 17 17:30:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1087069 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PNZl8wHy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44kq5n6cCLz9s5c for ; Thu, 18 Apr 2019 03:31:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729641AbfDQRbD (ORCPT ); Wed, 17 Apr 2019 13:31:03 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:36901 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733034AbfDQRaX (ORCPT ); Wed, 17 Apr 2019 13:30:23 -0400 Received: by mail-wm1-f66.google.com with SMTP id v14so4566831wmf.2; Wed, 17 Apr 2019 10:30:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b+YiUM75De4BFeN5CqwNUI+YVTIngpiY3A0fybpC1XI=; b=PNZl8wHyxbSAmvbzf4KiobddapYSMCxVKmxwk9lrMRnkVoGOtP+PKtfakTyBvpxJok AS8kfvF4EL7oM/w6sjWrEnSr+isSbCJjCB1UnUhrRTY2hnUtUehSaWSuofVL6gmL1Kba wYdufqWdWg1vts73uwTNWzymieHs1p7bpbti0Rt/2wbqBIc0bMkQIORYO1Nwygz7HlPw w3ujKcBqjrtn0m62RGKJacL/8Jd8VsIoKSUezoowq9zhS95+Cu22iwWv77G1YlNpHj1i GLHu0ySt8AEBSfOGmiUwMh9iraL9Ap13YHA1UPP7DO2G7m7sN5ZtTPzlvg5R5cjJWmBr nc2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b+YiUM75De4BFeN5CqwNUI+YVTIngpiY3A0fybpC1XI=; b=EL2V2Qn7w9cZ6q770Ta6qQt/bem1wvWYVWGcwyIigF2wag9JT7pTgAhu4va25apFPY zCpx5M0/WF8RvxLzzwsZ694fXOE1vcpvWx8yUIcpIno9bXHPsLWc93metNljUSmfBZ6k bEyYSn7vsXRMm/rPZD60hvJOiUPsUbVT4Pc8RPMEfVEpDpNn441u5AWi1I2kGuax6hZ/ q7VHxcY2hL+MHWYFZR1CD7nh7Xgk1zxikcHM017q2OKTQr/i5nD02unAYV6NBBNxBGEn 4indloUSOQwHlVKJsqsbhCSDI6idaYcRuTTt6AY7XVoJi9V7qWvGq0hY+6a9cofqZo5R ivJA== X-Gm-Message-State: APjAAAXrnShSq+Gx8GMyQ/4rnwginhjyJUdqEtiBVKa2x0tCDnNSZEdL QTsxyw4/fx4MOC+Epla037E= X-Google-Smtp-Source: APXvYqyCy70GDJ7gaJUnHBS5DgBh6IpUzbzie+xsxjtCGtR2KujMDcMaVi0NFQi7i/It4O55Ud+8KA== X-Received: by 2002:a1c:ca06:: with SMTP id a6mr33040526wmg.14.1555522221471; Wed, 17 Apr 2019 10:30:21 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id c6sm2669306wmb.21.2019.04.17.10.30.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 10:30:20 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Icenowy Zheng , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v3 2/8] dt-bindings: gpu: mali-midgard: Add bus clock bindings Date: Wed, 17 Apr 2019 19:30:25 +0200 Message-Id: <20190417173031.9920-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190417173031.9920-1-peron.clem@gmail.com> References: <20190417173031.9920-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Icenowy Zheng Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. + * core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) + * bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. From patchwork Wed Apr 17 17:30:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1087065 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WdDW/OIq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44kq502Rddz9s5c for ; Thu, 18 Apr 2019 03:30:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733068AbfDQRa0 (ORCPT ); Wed, 17 Apr 2019 13:30:26 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:53094 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733042AbfDQRaZ (ORCPT ); Wed, 17 Apr 2019 13:30:25 -0400 Received: by mail-wm1-f65.google.com with SMTP id a184so4348726wma.2; Wed, 17 Apr 2019 10:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kdl2HLHW70ntA/K0rj6AA2zlxJSYSzmovpJ45Rbdc0c=; b=WdDW/OIqEWCV869Zlk47vlcYn69NFnuxXYOpNiTsMOhdeW065WuDvBIpj46z4eey+Z CSm7Y3XIxb4jPKAoVGNj4DcZBmuRSV3ngRJqpCnoZB7bi9eyhRXz3YyX3GBBabZaU9bM CBDBtsa1q1jc9HJoS432wV4kQLwoLJ/na8JQ6DU/mk/M1gHMGRQeQ6HFUQXFeedkppB4 Q0rB1hvII6Fhul7M97Vcnnyahkr5oYk7Xb/uq9KXUB3UuQN/nIhx3/HZFlKWhPFld4Ha 4ocMhF8XsgwhtXfvVqdRSWCFaUEn9n3bhxpQ8QzW17cG0ikBycV2DKOGdezphkQJCqcS pnig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kdl2HLHW70ntA/K0rj6AA2zlxJSYSzmovpJ45Rbdc0c=; b=ifuqWjLLTW/FW1hUnxfq56tgNlFdynqi2G9omN0+HWg743hVGjjsrFDedX/Vty9WUd SGxjLN4qj6VjbfW+EVvoYZmZ1oR/NErdIOgcZGXS/QXoFx16YOpu+de5tmrhKlR15wC0 pBCivVeo72Gug0c+TT/ve51Oeb5swP70Xh9oAjJKVbKm5GG2F1JM4/NtCtlvEsl68yLy IFp5Ce1vMO0IkP4OeahrQ1+aU2ykvp6udkFN+QgBmrc0ANHYx7DDJhpHK24RCVu7Ml6R 4EKSIaHm95Wyz79wH52/xSo7JTSEB5U+jQpdyWCMD4cnZHqrYHgl7IIkswtwwWkw7QCK qhAg== X-Gm-Message-State: APjAAAXcJQXisGzDdX6N7tEd2IglzM6ss8Rjx49Za3l1s/QeB9a1xdvx WK6YiE1qELwrG2mTqj60beI= X-Google-Smtp-Source: APXvYqwyGY/wOiRSL0RJvXiA2emmo4L2E5scQmpjfBKtPTcLAMkig5bTub9IXtPSi7Ty8GxNH1cD2A== X-Received: by 2002:a7b:cb16:: with SMTP id u22mr601497wmj.60.1555522223267; Wed, 17 Apr 2019 10:30:23 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id c6sm2669306wmb.21.2019.04.17.10.30.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 10:30:22 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v3 3/8] dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible Date: Wed, 17 Apr 2019 19:30:26 +0200 Message-Id: <20190417173031.9920-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190417173031.9920-1-peron.clem@gmail.com> References: <20190417173031.9920-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..4bf17e1cf555 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: + + "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,15 @@ Vendor-specific bindings ------------------------ The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - clocks : phandles to core and bus clocks + - clock-names : must contain "core" and "bus" + - resets: phandle to GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of :