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APjAAAWcusMOyI3DyruLvVNJqHdwWOcTPZwBjrEyvYMrnmSlFQYr6QDx 7Fc4iR8uvDfTPyxwSeMhSthMyHoKVZOgTQ== X-Google-Smtp-Source: APXvYqwf4lHZ8DGhQCH+wztGFt/oy7NslHkj4fG9oAqzup6ZkpGNWfStYnldUGT6EIXpDi1Fag1Cxw== X-Received: by 2002:a1c:43c2:: with SMTP id q185mr20094122wma.53.1555317891756; Mon, 15 Apr 2019 01:44:51 -0700 (PDT) Received: from [173.194.76.108] ([149.199.62.129]) by smtp.gmail.com with ESMTPSA id z7sm48233405wrt.10.2019.04.15.01.44.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 01:44:50 -0700 (PDT) To: arm-soc From: Michal Simek Subject: [GIT PULL] arm64: dts: Xilinx DT changes for v5.2 Openpgp: preference=signencrypt Autocrypt: addr=monstr@monstr.eu; prefer-encrypt=mutual; keydata= mQINBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF 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-------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:32c listed in] [list.dnswl.org] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 DKIMWL_WL_MED DKIMwl.org - Medium sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: monstr@monstr.eu Cc: linux-arm Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Hi, please pull these patches to your tree. It is just 3 patches where two are related to firmware clock. One is file rename and second is binding doc separation. And the last is adding standard TI quirk to phy node. Thanks, Michal The following changes since commit 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b: Linux 5.1-rc1 (2019-03-17 14:22:26 -0700) are available in the git repository at: https://github.com/Xilinx/linux-xlnx.git tags/zynqmp-dt-for-v5.2 for you to fetch changes up to 78c484a55d915e36891be5bae92e516fdac8609d: arm64: zynqmp: dt: Add TI PHY quirk (2019-03-18 15:59:08 +0100) ---------------------------------------------------------------- arm64: dts: zynqmp: DT changes for v5.2 - Align xlnx-zynqmp-clk.h file name and separate binding for clock driver - Add TI quirks to zynqmp boards ---------------------------------------------------------------- Harini Katakam (1): arm64: zynqmp: dt: Add TI PHY quirk Jolly Shah (1): include: dt-binding: clock: Rename zynqmp header file Rajan Vaja (1): dt-bindings: xilinx: Separate clock binding from firmware doc Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt | 54 +----------------------------------------------------- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 + include/dt-bindings/clock/{xlnx,zynqmp-clk.h => xlnx-zynqmp-clk.h} | 26 ++++++++++++++++++-------- 9 files changed, 88 insertions(+), 61 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt rename include/dt-bindings/clock/{xlnx,zynqmp-clk.h => xlnx-zynqmp-clk.h} (85%)