From patchwork Thu Apr 11 10:19:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083830 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="oyGTc0BW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxrz70ffz9s3q for ; Thu, 11 Apr 2019 20:21:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726750AbfDKKT6 (ORCPT ); Thu, 11 Apr 2019 06:19:58 -0400 Received: from vps.xff.cz ([195.181.215.36]:48360 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726588AbfDKKT5 (ORCPT ); Thu, 11 Apr 2019 06:19:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977994; bh=unyXzRpGhfWJQ+WLXU6ly2jmSYKOT8hB+V2vSbRnR30=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oyGTc0BWzGcUxj5sXpJl9xAtrzl8WhcR6Nw7cxnwn+GA/FqkDQ9AfM1A/joxea4cJ TH4kjKGpOH/bZekEOz0mDJp5kEJqrtUKInT97MFB2NLiEvytdT6CtJo9cAOYD9QbFp EfaJQ6G7HGkx6tEaCZDJjezPOCM7UPA+ISgvN+CA= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Icenowy Zheng , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org, Ondrej Jirman Subject: [PATCH v3 01/11] net: stmmac: sun8i: add support for Allwinner H6 EMAC Date: Thu, 11 Apr 2019 12:19:41 +0200 Message-Id: <20190411101951.30223-2-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Icenowy Zheng The EMAC on Allwinner H6 is just like the one on A64. The "internal PHY" on H6 is on a co-packaged AC200 chip, and it's not really internal (it's connected via RMII at PA GPIO bank). Add support for the Allwinner H6 EMAC in the dwmac-sun8i driver. Signed-off-by: Icenowy Zheng Signed-off-by: Ondrej Jirman --- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 195669f550f0..20c19afb8316 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -147,6 +147,20 @@ static const struct emac_variant emac_variant_a64 = { .tx_delay_max = 7, }; +static const struct emac_variant emac_variant_h6 = { + .default_syscon_value = 0x50000, + .syscon_field = &sun8i_syscon_reg_field, + /* The "Internal PHY" of H6 is not on the die. It's on the + * co-packaged AC200 chip instead. + */ + .soc_has_internal_phy = false, + .support_mii = true, + .support_rmii = true, + .support_rgmii = true, + .rx_delay_max = 31, + .tx_delay_max = 7, +}; + #define EMAC_BASIC_CTL0 0x00 #define EMAC_BASIC_CTL1 0x04 #define EMAC_INT_STA 0x08 @@ -1210,6 +1224,8 @@ static const struct of_device_id sun8i_dwmac_match[] = { .data = &emac_variant_r40 }, { .compatible = "allwinner,sun50i-a64-emac", .data = &emac_variant_a64 }, + { .compatible = "allwinner,sun50i-h6-emac", + .data = &emac_variant_h6 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); From patchwork Thu Apr 11 10:19:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083833 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="Qto8jyUL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxs5675gz9s47 for ; Thu, 11 Apr 2019 20:21:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726713AbfDKKT6 (ORCPT ); Thu, 11 Apr 2019 06:19:58 -0400 Received: from vps.xff.cz ([195.181.215.36]:48398 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726677AbfDKKT5 (ORCPT ); Thu, 11 Apr 2019 06:19:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977995; bh=VCU/uAG/CGlp0N/Ie+gLjiEg/N8Z0m54HtEJgdiJHWQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Qto8jyULfncNvfKKRwPzZP1JB3/oy4HWo/AuWudxJaoV4XRfbiL6QW2mAHqd/xQu/ ZlQByk2qHZGItuf2QKJutUHdaK5OUA3xlj8ylEZUjHZr4LUEsEedHkPh3+bt3x86Qy DSWRXWKxCwJjHfzTsi2ig/zvmIn1HGfGP8ysOz8M= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Icenowy Zheng , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org, Ondrej Jirman Subject: [PATCH v3 02/11] net: stmmac: sun8i: force select external PHY when no internal one Date: Thu, 11 Apr 2019 12:19:42 +0200 Message-Id: <20190411101951.30223-3-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Icenowy Zheng The PHY selection bit also exists on SoCs without an internal PHY; if it's set to 1 (internal PHY, default value) then the MAC will not make use of any PHY such SoCs. This problem appears when adapting for H6, which has no real internal PHY (the "internal PHY" on H6 is not on-die, but on a co-packaged AC200 chip, connected via RMII interface at GPIO bank A). Force the PHY selection bit to 0 when the SOC doesn't have an internal PHY, to address the problem of a wrong default value. Signed-off-by: Icenowy Zheng Signed-off-by: Ondrej Jirman --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 20c19afb8316..cb7e7f53be7d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -907,6 +907,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) * address. No need to mask it again. */ reg |= 1 << H3_EPHY_ADDR_SHIFT; + } else { + /* For SoCs without internal PHY the PHY selection bit should be + * set to 0 (external PHY). + */ + reg &= ~H3_EPHY_SELECT; } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { From patchwork Thu Apr 11 10:19:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083828 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="jj4C1apl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxrr4t0Xz9s71 for ; Thu, 11 Apr 2019 20:21:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727191AbfDKKV2 (ORCPT ); Thu, 11 Apr 2019 06:21:28 -0400 Received: from vps.xff.cz ([195.181.215.36]:48438 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726678AbfDKKT6 (ORCPT ); Thu, 11 Apr 2019 06:19:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977995; bh=DdOJz/KUHvzyoOqY/X/p8VGDaZGkFFOEFng4t6EKayc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jj4C1aplFLTIhC+zesYBGtAgQarcYkxVN/3bdGBb6on/rJ3BytYOg8T5nHOIR2me7 ZxiqsSpiAQVKG1AmXYY6PB4+mjxspzXnWHLQL9icIf2jA8uDt22aUXsFxAaipBRG9i 8idxt9JEfJYf62x2x7cTjCFf0c3K4NJugm1yl4GQ= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 03/11] pinctrl: sunxi: Prepare for alternative bias voltage setting methods Date: Thu, 11 Apr 2019 12:19:43 +0200 Message-Id: <20190411101951.30223-4-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman H6 has a different I/O voltage bias setting method than A80. Prepare existing code for using alternative bias voltage setting methods. Signed-off-by: Ondrej Jirman --- drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 47 +++++++++++++---------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 9 ++++- 3 files changed, 36 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index da37d594a13d..0633a03d5e13 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { .npins = ARRAY_SIZE(sun9i_a80_pins), .irq_banks = 5, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index be04223591d4..98c4de5f4019 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -617,7 +617,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, u32 val, reg; int uV; - if (!pctl->desc->has_io_bias_cfg) + if (!pctl->desc->io_bias_cfg_variant) return 0; uV = regulator_get_voltage(supply); @@ -628,25 +628,32 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, if (uV == 0) return 0; - /* Configured value must be equal or greater to actual voltage */ - if (uV <= 1800000) - val = 0x0; /* 1.8V */ - else if (uV <= 2500000) - val = 0x6; /* 2.5V */ - else if (uV <= 2800000) - val = 0x9; /* 2.8V */ - else if (uV <= 3000000) - val = 0xA; /* 3.0V */ - else - val = 0xD; /* 3.3V */ - - pin -= pctl->desc->pin_base; - - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); - reg &= ~IO_BIAS_MASK; - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); - - return 0; + switch (pctl->desc->io_bias_cfg_variant) { + case BIAS_VOLTAGE_GRP_CONFIG: + /* + * Configured value must be equal or greater to actual + * voltage. + */ + if (uV <= 1800000) + val = 0x0; /* 1.8V */ + else if (uV <= 2500000) + val = 0x6; /* 2.5V */ + else if (uV <= 2800000) + val = 0x9; /* 2.8V */ + else if (uV <= 3000000) + val = 0xA; /* 3.0V */ + else + val = 0xD; /* 3.3V */ + + pin -= pctl->desc->pin_base; + + reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); + reg &= ~IO_BIAS_MASK; + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + return 0; + default: + return -EINVAL; + } } static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index ee15ab067b5f..4bfc8a6d9dce 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -95,6 +95,13 @@ #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +enum sunxi_desc_bias_voltage { + BIAS_VOLTAGE_NONE, + /* Bias voltage configuration is done through + * Pn_GRP_CONFIG registers, as seen on A80 SoC. */ + BIAS_VOLTAGE_GRP_CONFIG, +}; + struct sunxi_desc_function { unsigned long variant; const char *name; @@ -117,7 +124,7 @@ struct sunxi_pinctrl_desc { const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; - bool has_io_bias_cfg; + int io_bias_cfg_variant; }; struct sunxi_pinctrl_function { From patchwork Thu Apr 11 10:19:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083826 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="UZ/3N3NX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxrb3y46z9s3q for ; Thu, 11 Apr 2019 20:21:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727167AbfDKKVO (ORCPT ); Thu, 11 Apr 2019 06:21:14 -0400 Received: from vps.xff.cz ([195.181.215.36]:48474 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726680AbfDKKT7 (ORCPT ); Thu, 11 Apr 2019 06:19:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977996; bh=//Y9g6FyC9JeT0oJjFckG39umOxcy3nQRVaTbv9yQdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UZ/3N3NXudgSWaEaZ1WVknpjen7QYUsm4mZNrs58RmLQ18Ej7tvtbPgC6oq7sKny9 2XVrvVT34Wjo64BNOwZHuiV6o+DGFfcFQ7O1PdrXXffByd+rm0l/veBWY4GstRbEYN c9wniYueWtPlirCLW3VcFr3X1C3sR8EDNRzkeANc= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 04/11] pinctrl: sunxi: Support I/O bias voltage setting on H6 Date: Thu, 11 Apr 2019 12:19:44 +0200 Message-Id: <20190411101951.30223-5-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman H6 SoC has a "pio group withstand voltage mode" register (datasheet description), that needs to be used to select either 1.8V or 3.3V I/O mode, based on what voltage is powering the respective pin banks and is thus used for I/O signals. Add support for configuring this register according to the voltage of the pin bank regulator (if enabled). This is similar to the support for I/O bias voltage setting patch for A80 and the same concerns apply. See: commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") Signed-off-by: Ondrej Jirman Acked-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 11 +++++++++++ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c index ef4268cc6227..3cc1121589c9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { .irq_banks = 4, .irq_bank_map = h6_irq_bank_map, .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; static int h6_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 98c4de5f4019..0cbca30b75dc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, unsigned pin, struct regulator *supply) { + unsigned short bank = pin / PINS_PER_BANK; + unsigned long flags; u32 val, reg; int uV; @@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, reg &= ~IO_BIAS_MASK; writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); return 0; + case BIAS_VOLTAGE_PIO_POW_MODE_SEL: + val = uV <= 1800000 ? 1 : 0; + + raw_spin_lock_irqsave(&pctl->lock, flags); + reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); + reg &= ~(1 << bank); + writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); + raw_spin_unlock_irqrestore(&pctl->lock, flags); + return 0; default: return -EINVAL; } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 4bfc8a6d9dce..36186906f0a7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -95,11 +95,16 @@ #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +#define PIO_POW_MOD_SEL_REG 0x340 + enum sunxi_desc_bias_voltage { BIAS_VOLTAGE_NONE, /* Bias voltage configuration is done through * Pn_GRP_CONFIG registers, as seen on A80 SoC. */ BIAS_VOLTAGE_GRP_CONFIG, + /* Bias voltage is set through PIO_POW_MOD_SEL_REG + * register, as seen on H6 SoC, for example. */ + BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; struct sunxi_desc_function { From patchwork Thu Apr 11 10:19:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083818 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="jnLgY6hj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxr35737z9s3q for ; Thu, 11 Apr 2019 20:20:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727057AbfDKKUl (ORCPT ); Thu, 11 Apr 2019 06:20:41 -0400 Received: from vps.xff.cz ([195.181.215.36]:48596 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726770AbfDKKUB (ORCPT ); Thu, 11 Apr 2019 06:20:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977996; bh=IsaR7dDt8nOTyMWc3EVZ7VXz2M/dDBLCBbhMC8cbWJY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jnLgY6hjCJohILqwFAXKl6dPqfw/6qsQj7ifGAUTOoU7873CeYzCQUUSj7ZRCQolu pgRoWbDzwgf96DAcDneMWUsRz46Yi1wfwzxtiYD4rC3uK7gh/D3GoA7F/2ICbQ+2Si l0npHr7A+46ySSMJwFUMzaqo+IfaiuIV6mTJoUBc= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 05/11] arm64: dts: allwinner: orange-pi-3: Enable ethernet Date: Thu, 11 Apr 2019 12:19:45 +0200 Message-Id: <20190411101951.30223-6-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E. According to the phy datasheet, both regulators need to be enabled at the same time, but we can only specify a single phy-supply in the DT. This can be achieved by making one regulator depedning on the other via vin-supply. While it's not a technically correct description of the hardware, it achieves the purpose. All values of RX/TX delay were tested exhaustively and a middle one of the working values was chosen. Signed-off-by: Ondrej Jirman --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 17d496990108..6d6b1f66796d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -15,6 +15,7 @@ aliases { serial0 = &uart0; + ethernet0 = &emac; }; chosen { @@ -44,6 +45,27 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2) power rails + * at the same time and to wait 100ms. + */ + reg_gmac_2v5: gmac-2v5 { + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + + /* The real parent of gmac-2v5 is reg_vcc5v, but we need to + * enable two regulators to power the phy. This is one way + * to achieve that. + */ + vin-supply = <®_aldo2>; /* GMAC-3V3 */ + }; }; &cpu0 { @@ -58,6 +80,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_gmac_2v5>; + allwinner,rx-delay-ps = <1500>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ From patchwork Thu Apr 11 10:19:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083819 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="rShVtDlm"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxr65Lc7z9s71 for ; Thu, 11 Apr 2019 20:20:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727041AbfDKKUl (ORCPT ); Thu, 11 Apr 2019 06:20:41 -0400 Received: from vps.xff.cz ([195.181.215.36]:48598 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726677AbfDKKUB (ORCPT ); Thu, 11 Apr 2019 06:20:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977997; bh=5oK+hUHvbPopzw2Jlb3qkR0ZnXTFnDc3XhhaDlcdJng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rShVtDlmYfsIffqn52CiTS0aaDYBAlJANuq/YRzukRqIi6d1SHXabea4uVW760pay pRvWPTfEPjc35EVA0vxz1Z3ShtAi/MtrfsKdGGcO1IIzWgcFL5whEH8Ecyyg5cPrNY BG6r3ulcBnlaCmXGbi7JFMwfMelCwQkTqSPPcVyY= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 06/11] dt-bindings: display: hdmi-connector: Add DDC power supply Date: Thu, 11 Apr 2019 12:19:46 +0200 Message-Id: <20190411101951.30223-7-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Some Allwinner SoC using boards (Orange Pi 3 for example) need to enable on-board voltage shifting logic for the DDC bus to be usable. Use ddc-supply on the hdmi-connector to model this. Add binding documentation for optional ddc-supply property. Signed-off-by: Ondrej Jirman --- .../devicetree/bindings/display/connector/hdmi-connector.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt index 508aee461e0d..33085aeb0bb9 100644 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt +++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt @@ -9,6 +9,7 @@ Optional properties: - label: a symbolic name for the connector - hpd-gpios: HPD GPIO number - ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing +- ddc-supply: the power supply for the DDC bus Required nodes: - Video port for HDMI input From patchwork Thu Apr 11 10:19:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083821 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="SC6T5zFH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxrF0BzRz9s3q for ; Thu, 11 Apr 2019 20:21:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727004AbfDKKUk (ORCPT ); Thu, 11 Apr 2019 06:20:40 -0400 Received: from vps.xff.cz ([195.181.215.36]:48608 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726775AbfDKKUD (ORCPT ); Thu, 11 Apr 2019 06:20:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977997; bh=6VLGBninVYhLf3SKuzVOvcFENaFxMRjZ/uyrW9t0ZFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SC6T5zFHak+HH758QTiX/0XdsteacPTzOO0BLxDh/pqZwl943jaz3s/nZICaiTPmp UkO0sF/Ggir//tPrEm1F3Wx6h3TSe4UAebDkyUgVgGFr3xRZIjJQ5jzdV5yQuq4d1d VNeQqNnGcT1QRDYPHwQQd/NG8lV2XqN/r0+csXWA= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 07/11] drm: sun4i: Add support for enabling DDC I2C bus power to dw_hdmi glue Date: Thu, 11 Apr 2019 12:19:47 +0200 Message-Id: <20190411101951.30223-8-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Orange Pi 3 board requires enabling DDC I2C bus via some GPIO connected transistors, before the bus can be used. Model this as a power supply for DDC bus on the HDMI connector connected to the output port (port 1) of the HDMI controller. Signed-off-by: Ondrej Jirman --- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 60 ++++++++++++++++++++++++++- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 + 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c index 39d8509d96a0..1b6ffba41177 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c @@ -98,6 +98,30 @@ static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, return crtcs; } +static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev, + struct platform_device **pdev_out) +{ + struct platform_device* pdev; + struct device_node *remote; + + remote = of_graph_get_remote_node(dev->of_node, 1, -1); + if (!remote) + return -ENODEV; + + if (!of_device_is_compatible(remote, "hdmi-connector")) { + of_node_put(remote); + return -ENODEV; + } + + pdev = of_find_device_by_node(remote); + of_node_put(remote); + if (!pdev) + return -ENODEV; + + *pdev_out = pdev; + return 0; +} + static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, void *data) { @@ -151,16 +175,34 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, return PTR_ERR(hdmi->regulator); } + ret = sun8i_dw_hdmi_find_connector_pdev(dev, &hdmi->connector_pdev); + if (!ret) { + hdmi->ddc_regulator = regulator_get(&hdmi->connector_pdev->dev, "ddc"); + if (IS_ERR(hdmi->ddc_regulator)) { + platform_device_put(hdmi->connector_pdev); + dev_err(dev, "Couldn't get ddc regulator\n"); + return PTR_ERR(hdmi->ddc_regulator); + } + } + ret = regulator_enable(hdmi->regulator); if (ret) { dev_err(dev, "Failed to enable regulator\n"); - return ret; + goto err_unref_ddc_regulator; + } + + if (hdmi->ddc_regulator) { + ret = regulator_enable(hdmi->ddc_regulator); + if (ret) { + dev_err(dev, "Failed to enable ddc regulator\n"); + goto err_disable_regulator; + } } ret = reset_control_deassert(hdmi->rst_ctrl); if (ret) { dev_err(dev, "Could not deassert ctrl reset control\n"); - goto err_disable_regulator; + goto err_disable_ddc_regulator; } ret = clk_prepare_enable(hdmi->clk_tmds); @@ -213,8 +255,15 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, clk_disable_unprepare(hdmi->clk_tmds); err_assert_ctrl_reset: reset_control_assert(hdmi->rst_ctrl); +err_disable_ddc_regulator: + if (hdmi->ddc_regulator) + regulator_disable(hdmi->ddc_regulator); err_disable_regulator: regulator_disable(hdmi->regulator); +err_unref_ddc_regulator: + if (hdmi->ddc_regulator) + regulator_put(hdmi->ddc_regulator); + platform_device_put(hdmi->connector_pdev); return ret; } @@ -229,6 +278,13 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, clk_disable_unprepare(hdmi->clk_tmds); reset_control_assert(hdmi->rst_ctrl); regulator_disable(hdmi->regulator); + + if (hdmi->ddc_regulator) { + regulator_disable(hdmi->ddc_regulator); + regulator_put(hdmi->ddc_regulator); + } + + platform_device_put(hdmi->connector_pdev); } static const struct component_ops sun8i_dw_hdmi_ops = { diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 720c5aa8adc1..60f5200aee73 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -188,8 +188,10 @@ struct sun8i_dw_hdmi { struct sun8i_hdmi_phy *phy; struct dw_hdmi_plat_data plat_data; struct regulator *regulator; + struct regulator *ddc_regulator; const struct sun8i_dw_hdmi_quirks *quirks; struct reset_control *rst_ctrl; + struct platform_device *connector_pdev; }; static inline struct sun8i_dw_hdmi * From patchwork Thu Apr 11 10:19:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083809 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="j0iRJk61"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxqC4gkFz9sB3 for ; Thu, 11 Apr 2019 20:20:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726856AbfDKKUF (ORCPT ); Thu, 11 Apr 2019 06:20:05 -0400 Received: from vps.xff.cz ([195.181.215.36]:48628 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726783AbfDKKUD (ORCPT ); Thu, 11 Apr 2019 06:20:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977997; bh=k+NFW5pnNye36nApqt9JrO71mvvDIYVukOTYPbvyx1M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j0iRJk61GDGLkWr6mQFSzMCUVtteL54tuiyUIlf3mnHQTv/MGFWO511lce0iUcvuA mThmZdJI0LKS8i3dohUEy3dSIiAzAyLYM1NL+H/IidT1pkANDFlgKbpOvovQmE3+LO h388K2BEa03/w6iEVW0gjSHGoOZ5tiEGLOwJ5tos= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 08/11] arm64: dts: allwinner: orange-pi-3: Enable HDMI output Date: Thu, 11 Apr 2019 12:19:48 +0200 Message-Id: <20190411101951.30223-9-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high. Signed-off-by: Ondrej Jirman --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 6d6b1f66796d..58a6635c909e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -22,6 +22,18 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + ddc-supply = <®_ddc>; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -37,6 +49,15 @@ }; }; + reg_ddc: ddc-io { + compatible = "regulator-fixed"; + regulator-name = "ddc-io"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + }; + reg_vcc5v: vcc5v { /* board wide 5V supply directly from the DC jack */ compatible = "regulator-fixed"; @@ -72,6 +93,10 @@ cpu-supply = <®_dcdca>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -91,6 +116,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; From patchwork Thu Apr 11 10:19:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083811 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="XGJOQLMJ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxqL0jR5z9s7h for ; Thu, 11 Apr 2019 20:20:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726874AbfDKKUG (ORCPT ); Thu, 11 Apr 2019 06:20:06 -0400 Received: from vps.xff.cz ([195.181.215.36]:48654 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbfDKKUD (ORCPT ); Thu, 11 Apr 2019 06:20:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977998; bh=op3dm3pge3hkv+pHZJvJy03uxi6x4i/4K3sT0Q5NnKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XGJOQLMJkpSslkwXm/VvU2qMpf5vs/sEjdq53pbLv8HN7S3nguc0HDTkamrHDeEJN g7vsLIAh9igd4Ia8B3vyCEEP1+ST8NLNgZt6xUKTdL61z6YBWDnehLY99k8X7Z7jYA 5MvQYo4TYYE165L6ACC9fNVLSf4NOlA2oax7Dfig= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 09/11] brcmfmac: Loading the correct firmware for brcm43456 Date: Thu, 11 Apr 2019 12:19:49 +0200 Message-Id: <20190411101951.30223-10-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman SDIO based brcm43456 is currently misdetected as brcm43455 and the wrong firmware name is used. Correct the detection and load the correct firmware file. Chiprev for brcm43456 is "9". Signed-off-by: Ondrej Jirman --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c index a06af0cd4a7f..22b73da42822 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c @@ -622,6 +622,7 @@ BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); /* Note the names are not postfixed with a1 for backward compatibility */ BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio"); BRCMF_FW_DEF(43455, "brcmfmac43455-sdio"); +BRCMF_FW_DEF(43456, "brcmfmac43456-sdio"); BRCMF_FW_DEF(4354, "brcmfmac4354-sdio"); BRCMF_FW_DEF(4356, "brcmfmac4356-sdio"); BRCMF_FW_DEF(4373, "brcmfmac4373-sdio"); @@ -642,7 +643,8 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1), - BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455), + BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456), + BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455), BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373), From patchwork Thu Apr 11 10:19:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083814 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="degI29QP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxqd5BX2z9s47 for ; Thu, 11 Apr 2019 20:20:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726952AbfDKKU2 (ORCPT ); Thu, 11 Apr 2019 06:20:28 -0400 Received: from vps.xff.cz ([195.181.215.36]:48720 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726808AbfDKKUE (ORCPT ); Thu, 11 Apr 2019 06:20:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977998; bh=ZOGzdottk2RIleoufnn4ifjkGAGSzeCzkeoCu7y/pEo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=degI29QP7YcQKyPUxemM2IX9aelSS2lzM+LB7J5Lwuq4jETxcCofSDshcwqSgtn27 pYOjNtuwuBo/JfYwWEpOsaPJNNug+N/qC9u/A/DEsOvcDEajouZ1KAWnd4Qqp7vOOW zVaeomVuAfHe6XGBAwpoz6tPlavhKMf9a/95eydQ= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 10/11] arm64: dts: allwinner: h6: Add MMC1 pins Date: Thu, 11 Apr 2019 12:19:50 +0200 Message-Id: <20190411101951.30223-11-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman MMC1 is used on some H6 boards we want to support. Typical use is 4-bit SDIO interface with a WiFi chip. Add pin definitions for this use case. As this is the only possible configration for mmc1, make it the default one, too. Signed-off-by: Ondrej Jirman --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index e0dc4a05c1ba..bd37b849d3b7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -243,6 +243,15 @@ bias-pull-up; }; + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_pins: mmc2-pins { pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", @@ -294,6 +303,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; From patchwork Thu Apr 11 10:19:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1083812 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="pKnQJw63"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fxqX2HXWz9s47 for ; Thu, 11 Apr 2019 20:20:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726913AbfDKKUS (ORCPT ); Thu, 11 Apr 2019 06:20:18 -0400 Received: from vps.xff.cz ([195.181.215.36]:48774 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726813AbfDKKUF (ORCPT ); Thu, 11 Apr 2019 06:20:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977999; bh=RlyawPV8DdQgLhoOmv75silSjjlBNuFMgDCcJui9Css=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pKnQJw63o7G2MAK5Wdr3kFoE1R27AJTayB4b5VEHCvXQc3sQ4AqiilAwA2u++oOXL p2YvKUyRna5cIpqZwxeWpYsTaRxJyO0fb8xiPJMI+3HSTZVbw72/OWefciQULQdG4H knB2eQn1fqabs3I2aSVVmNVNQQVNy2dfECEQQbh8= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 11/11] [DO NOT MERGE] arm64: dts: allwinner: orange-pi-3: Enable WiFi Date: Thu, 11 Apr 2019 12:19:51 +0200 Message-Id: <20190411101951.30223-12-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called bcm43356 and can be used with the brcmfmac driver. The module is powered by the two always on regulators (not AXP805). WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be configured so that it sets up an 1.8V input bias on this port. This is done by the pio driver by reading the vcc-pg-supply voltage. You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt configuration that can be found in the Xulongs's repository for H6: https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 Mainline brcmfmac driver expects the firmware and nvram at the following paths relative to the firmware directory: brcm/brcmfmac43456-sdio.bin brcm/brcmfmac43456-sdio.txt Signed-off-by: Ondrej Jirman --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 58a6635c909e..f795362f5b77 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -67,6 +67,26 @@ regulator-always-on; }; + reg_vcc33_wifi: vcc33-wifi { + /* Always on 3.3V regulator for WiFi and BT */ + compatible = "regulator-fixed"; + regulator-name = "vcc33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; + + reg_vcc_wifi_io: vcc-wifi-io { + /* Always on 1.8V/300mA regulator for WiFi and BT IO */ + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_vcc33_wifi>; + }; + /* * The board uses 2.5V RGMII signalling. Power sequence to enable * the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2) power rails @@ -87,6 +107,14 @@ */ vin-supply = <®_aldo2>; /* GMAC-3V3 */ }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; }; &cpu0 { @@ -144,6 +172,25 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_vcc33_wifi>; + vqmmc-supply = <®_vcc_wifi_io>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcm: sdio-wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names = "host-wake"; + }; +}; + &ohci0 { status = "okay"; }; @@ -155,6 +202,7 @@ &pio { vcc-pc-supply = <®_bldo2>; vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_vcc_wifi_io>; }; &r_i2c {