From patchwork Thu Apr 11 08:43:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 1083765 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="Kgr6CJjA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fvgm73VMz9s3q for ; Thu, 11 Apr 2019 18:43:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727019AbfDKInb (ORCPT ); Thu, 11 Apr 2019 04:43:31 -0400 Received: from mail-pg1-f179.google.com ([209.85.215.179]:45247 "EHLO mail-pg1-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726649AbfDKInb (ORCPT ); Thu, 11 Apr 2019 04:43:31 -0400 Received: by mail-pg1-f179.google.com with SMTP id y3so3169048pgk.12 for ; Thu, 11 Apr 2019 01:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JqHO8lKeM93haURO5R5tVecQJ8UbH1Kcw/Zab79L6Eo=; b=Kgr6CJjAYBSxyonIFQu5rNUAZvcTHIQwudpmELNC7yENvka64jmGeyFcnpd737baLm 1h63lHGgT6Qx+ZMeMlVjJeiSGi7AnZD2EVy/ZRKbSovA6GYP6KvnWhPC6ln0Rnq7JBTj fjZU6Uhjh19wQRYMSmbnQMzg9frYd5FOEtM2aT0msi8ze1zybqeRP2LAZ30zm0c7Y1pK qxOH4DYO48oPUA5lrKNQ3arCiOqboIdV/RN7XQjNLTvivuB4fVaEi7qa98n1p7qrtUbg +aysP33pjlGcHfUbDwCZMF02zfYHvJJn5yI4mZwNRz9DQ1WLSkttVaf53x0rTEjHuD71 ZhtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JqHO8lKeM93haURO5R5tVecQJ8UbH1Kcw/Zab79L6Eo=; b=Sqj8uxh5ocKlOwGQUB6MDMgdvetik0i02xr7Rcsu1/KsQZmWUkOiKtKQ2fmC4qkJ1m NBdoLjR8JTBQqt2rGGzf1d33PB3W9u7pBj5GnhYhsIzcC8CBD6em0UuCy3Y3aA3L91bX a3Np8f7FSYa+jZtN+ISOyJVB5xvNfFfkq5WxMHK1cbGEkbQZB7YgvtslqaYWRn8NoHZ7 Eyh8ZnuA1xWeD8xcP/UhOv/DASdsmyMZfPhWKSxrSxyOEkyZ0gyENNueT8nMJJWPvRrp 8Qmd/fXGJIjzWZbkIYsyvzgYHb3rZJxC/xvq3Wdycv0niWSEZ9Dfc+QhlVb5+BKPn25r dKiw== X-Gm-Message-State: APjAAAWdhSM9rjp9YdZ2fUxDxeTS0KY3Ke/MOAbJ7L4KG42hy/qROQF+ uPQMg0WAAP/Jxmi5oQVp4mBalA== X-Google-Smtp-Source: APXvYqyILngJUeKvAkhBQwQyGvruEDKBmzAJ80hxuYFdNukeTQmUPgMamthwTe2deeanGqvmF1O+Kw== X-Received: by 2002:a62:e10e:: with SMTP id q14mr47618676pfh.161.1554972210998; Thu, 11 Apr 2019 01:43:30 -0700 (PDT) Received: from viisi.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a3sm61699456pfn.182.2019.04.11.01.43.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 01:43:30 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: Paul Walmsley , Paul Walmsley , Rob Herring , Mark Rutland , Palmer Dabbelt , Albert Ou Subject: [PATCH 2/6] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Date: Thu, 11 Apr 2019 01:43:00 -0700 Message-Id: <20190411084304.5072-3-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411084304.5072-2-paul.walmsley@sifive.com> References: <20190411084304.5072-2-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add YAML DT binding documentation for the SiFive FU540 SoC. This SoC is documented at: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Albert Ou Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- .../devicetree/bindings/riscv/sifive.yaml | 26 +++++++++++++++++++ MAINTAINERS | 9 +++++++ 2 files changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml new file mode 100644 index 000000000000..d2808d8d79bb --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive/sifive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive SoC-based boards + +maintainers: + - Paul Walmsley + - Palmer Dabbelt + +description: + SiFive SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - sifive,freedom-unleashed-a00-fu540 + - sifive,freedom-unleashed-a00 + - const: sifive,fu540-c000 + - const: sifive,fu540 +... diff --git a/MAINTAINERS b/MAINTAINERS index 3ec37f17f90e..c02bf352a8c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14138,6 +14138,15 @@ S: Supported K: sifive N: sifive +SIFIVE FU540 SYSTEM-ON-CHIP +M: Paul Walmsley +M: Palmer Dabbelt +L: linux-riscv@lists.infradead.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git +S: Supported +K: fu540 +N: fu540 + SILEAD TOUCHSCREEN DRIVER M: Hans de Goede L: linux-input@vger.kernel.org From patchwork Thu Apr 11 08:43:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 1083766 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="a0b5q2Kc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fvgy0K94z9s70 for ; Thu, 11 Apr 2019 18:43:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726938AbfDKInk (ORCPT ); Thu, 11 Apr 2019 04:43:40 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:34873 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726564AbfDKInk (ORCPT ); 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Thu, 11 Apr 2019 01:43:39 -0700 (PDT) Received: from viisi.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a3sm61699456pfn.182.2019.04.11.01.43.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 01:43:38 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: Paul Walmsley , Paul Walmsley , Rob Herring , Mark Rutland , Lorenzo Pieralisi Subject: [PATCH 3/6] dt-bindings: riscv: convert cpu binding to json-schema Date: Thu, 11 Apr 2019 01:43:01 -0700 Message-Id: <20190411084304.5072-4-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411084304.5072-2-paul.walmsley@sifive.com> References: <20190411084304.5072-2-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At Rob's request, we're starting to migrate our DT binding documentation to json-schema YAML format. Start by converting our cpu binding documentation. While doing so, document more properties and nodes. This includes adding binding documentation support for the E51 and U54 CPU cores ("harts") that are present on this SoC. These cores are described in: https://static.dev.sifive.com/FU540-C000-v1.0.pdf This cpus.yaml file is intended to be a starting point and to evolve over time. It passes dt-doc-validate as of the yaml-bindings commit 4c79d42e9216. This patch was originally based on the ARM json-schema binding documentation as added by commit 672951cbd1b7 ("dt-bindings: arm: Convert cpu binding to json-schema"). Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Lorenzo Pieralisi Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-riscv@lists.infradead.org --- .../devicetree/bindings/riscv/cpus.yaml | 274 ++++++++++++++++++ 1 file changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml new file mode 100644 index 000000000000..11ade807fd49 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -0,0 +1,274 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V bindings for 'cpus' DT nodes + +maintainers: + - Paul Walmsley + - Palmer Dabbelt + +description: |+ + In SoC device tree data files, the layout of CPUs is described in + the "cpus" node. This node in turn contains a number of subnodes + representing CPUs, which define properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + + with updates for RISC-V cores provided in this document. + + ================================ + Convention used in this document + ================================ + + This document follows the conventions described in the Devicetree + Specification, with the addition: + + - square brackets define bitfields, e.g. reg[7:0] represents the + value of the bitfield in the reg property contained in bits 7 down + to 0 + + ===================================== + cpus and cpu node bindings definition + ===================================== + + If a Devicetree file is used to provide hardware data to the kernel, + the RISC-V architecture requires the cpus and cpu nodes to be + present and contain the properties described below. + +properties: + $nodename: + const: cpus + description: Container of cpu nodes + + '#address-cells': + const: 1 + description: | + A single unsigned 32-bit integer uniquely identifies + each RISC-V hart in a system. (See the "reg" node under + the "cpu" node, below). + + '#size-cells': + const: 0 + +patternProperties: + '^cpu@[0-9a-f]+$': + properties: + device_type: + const: cpu + + reg: + maxItems: 1 + description: | + Set the "reg" property to the hart ID of this CPU node. + Each value in this property must be unique in the scope + of the Devicetree file that contains it. + + compatible: + items: + - const: riscv + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + description: | + Identifies that the hart uses the RISC-V instruction set + and identifies the type of the hart. + + mmu-type: + items: + - enum: + - riscv,sv32 + - riscv,sv39 + - riscv,sv48 + description: | + Identifies the MMU address translation mode used on this + hart. These values originate from the RISC-V Privileged + Specification document, available from + https://riscv.org/specifications/ + + riscv,isa: + items: + - enum: + - rv64imac + - rv64imafdc + description: | + Identifies the specific RISC-V instruction set architecture + supported by the hart. These are documented in the RISC-V + User-Level ISA document, available from + https://riscv.org/specifications/ + + The RISC-V Linux port only will execute on a subset of these + values. However, other hart cores may be present in the + Devicetree hardware description file that do not run Linux. + + timebase-frequency: + maxItems: 1 + description: | + Specifies the clock frequency of the system timer in Hz. + This value is common to all harts in this Linux system image. + + i-cache-block-size: + maxItems: 1 + description: | + Specifies the size, in bytes, of an instruction cache line. + + i-cache-sets: + maxItems: 1 + description: | + Specifies the number of sets in the hart's instruction cache. + + i-cache-size: + maxItems: 1 + description: | + Specifies the size, in bytes, of the hart's instruction cache. + + i-tlb-sets: + maxItems: 1 + description: | + Specifies the number of sets in the hart's instruction TLB. + If present, the "tlb-split" property must be set. + + i-tlb-size: + maxItems: 1 + description: | + Specifies the number of entries in the hart's instruction TLB. + If present, the "tlb-split" property must be set. + + d-cache-block-size: + maxItems: 1 + description: | + Specifies the size, in bytes, of a data cache line. + + d-cache-sets: + maxItems: 1 + description: | + Specifies the number of sets in the hart's data cache. + + d-cache-size: + maxItems: 1 + description: | + Specifies the size, in bytes, of the hart's data cache. + + d-tlb-sets: + maxItems: 1 + description: | + Specifies the number of sets in the hart's data TLB. + If present, the "tlb-split" property must be set. + + d-tlb-size: + maxItems: 1 + description: | + Specifies the number of entries in the hart's data TLB. + If present, the "tlb-split" property must be set. + + tlb-split: true + + patternProperties: + '^interrupt-controller@[0-9a-f]+$': + properties: + $nodename: + const: interrupt-controller + description: Describes the CPU's local interrupt controller + + '#interrupt-cells': + const: 1 + + compatible: + const: riscv,cpu-intc + + interrupt-controller: true + + required: + - '#interrupt-cells' + - compatible + - interrupt-controller + + required: + - device_type + - reg + - compatible + - riscv,isa + - timebase-frequency + +required: + - '#address-cells' + - '#size-cells' + +examples: + - | + // Example 1: SiFive Freedom U540G Development Kit + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + sifive,dtim = <&L8>; + sifive,itim = <&L7>; + status = "okay"; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + L13: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + - | + // Example 2: Spike ISA Simulator with 1 Hart + cpus { + cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; +...