From patchwork Thu Apr 11 08:27:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 1083758 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="A73YNgB9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fvL53rNVz9s71 for ; Thu, 11 Apr 2019 18:28:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726867AbfDKI2M (ORCPT ); Thu, 11 Apr 2019 04:28:12 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:44546 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726121AbfDKI2L (ORCPT ); Thu, 11 Apr 2019 04:28:11 -0400 Received: by mail-pg1-f194.google.com with SMTP id i2so3151596pgj.11 for ; Thu, 11 Apr 2019 01:28:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fs9k/ofObdjUeCTYkQB8LCaYi1pDWe1mex0AK1YWiFM=; b=A73YNgB9Tlzp9/1ThMjQJzZ0XzoiY6z0aCZiR9tfQL7lugFQtA5YSHA12G0l9wcrhN g1I06uRFoajRwB8nN2WVL7pacMNFhyJLNnAjvUCS/yMky9IPQcSw6KzlzVOisnSy5wJg SRztDTZh1UXWXh6RfYhhZpWe0bx18XLeTwRm1fsZgUkja3ESOHwaF+eOtdYZT9W4Jif1 e5JivajHWeGWsBrxbHAHZqRVPt3i9WxGNAvJ+DSIdUoI+U+4yfXmo8pM/0ZCfIhnoy/o bInuPxH3WxGVPmWYSowlA48Qx4zxLHhBhNXJCrhLIvA4nUbPisLN2FuqZdrEm+S6lD35 kNvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fs9k/ofObdjUeCTYkQB8LCaYi1pDWe1mex0AK1YWiFM=; b=NxSswvOT+LOTIjMy7FgeGHfBA9rEfx0studOwslTdlsXbePpSs7a3p7tWd2BvBexMn f2z0+vO0Y7nU5F6Sh8zEiC5e777PB5nuwaMw1jbnFM1XpP/35DYbkhG+L+FZCfGpo6Cs QqW68ZnF9VwcwjQCFGw4DM3wcMae2XxeTTUYscSL7L4+cmOLbirVRWAtH4FJ+TtDBvys 3Ubsu8+05HqBNx2quaxsjzYQOjkzWhvshwHV1vZ59zTKkutNZcaO+++9tHj5GNgdohdo Ac3IJBsLW2AUyLMy2h6t+6YTLHtyGYdnFDxd4FuUOgrtqyehDyI2f6NH0AhJe2Z7wceD YU6A== X-Gm-Message-State: APjAAAVcu27aBLDeSiOX67x3kbUrnK0zjTTVEVgdpgqV5TEAgmEBFeUI yMO/5rlSqusBjojRbYeSR6t7kg== X-Google-Smtp-Source: APXvYqzUVRFPufaj+05dU9sy/fCHaliilqvViAD6XI3gLfNv0DolX8Rzu1wfYKffz2EBgaRfSABbhQ== X-Received: by 2002:aa7:8609:: with SMTP id p9mr48274019pfn.166.1554971291183; Thu, 11 Apr 2019 01:28:11 -0700 (PDT) Received: from viisi.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id x28sm41043430pgl.38.2019.04.11.01.28.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 01:28:10 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Paul Walmsley , Paul Walmsley , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Palmer Dabbelt , Megan Wachs Subject: [PATCH v3 2/3] dt-bindings: clk: add documentation for the SiFive PRCI driver Date: Thu, 11 Apr 2019 01:27:34 -0700 Message-Id: <20190411082733.3736-3-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411082733.3736-2-paul.walmsley@sifive.com> References: <20190411082733.3736-2-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for the Linux driver for the SiFive PRCI clock & reset control IP block, as found on the SiFive FU540 chip. This version includes changes requested by Stephen Boyd and Rob Herring , and fixes some errors in the initial version. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Megan Wachs Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring --- .../bindings/clock/sifive/fu540-prci.txt | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt new file mode 100644 index 000000000000..349808f4fb8c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt @@ -0,0 +1,46 @@ +SiFive FU540 PRCI bindings + +On the FU540 family of SoCs, most system-wide clock and reset integration +is via the PRCI IP block. + +Required properties: +- compatible: Should be "sifive,-prci". Only one value is + supported: "sifive,fu540-c000-prci" +- reg: Should describe the PRCI's register target physical address region +- clocks: Should point to the hfclk device tree node and the rtcclk + device tree node. The RTC clock here is not a time-of-day clock, + but is instead a high-stability clock source for system timers + and cycle counters. +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock via the clock ID +macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. +These macros begin with PRCI_CLK_. + +The hfclk and rtcclk nodes are required, and represent physical +crystals or resonators located on the PCB. These nodes should be present +underneath /, rather than /soc. + +Examples: + +/* under /, in PCB-specific DT data */ +hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; +}; +rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; +}; + +/* under /soc, in SoC-specific DT data */ +prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; +};