From patchwork Wed Apr 10 23:25:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1083669 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qxAiqn45"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fg4Q6sd8z9s6w for ; Thu, 11 Apr 2019 09:15:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726826AbfDJXPd (ORCPT ); Wed, 10 Apr 2019 19:15:33 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:36017 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726096AbfDJXPc (ORCPT ); Wed, 10 Apr 2019 19:15:32 -0400 Received: by mail-wr1-f68.google.com with SMTP id y13so4862435wrd.3; Wed, 10 Apr 2019 16:15:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=qxAiqn45+6Y6QrCOAT+10PSRnzGB7LKozH2AtUj3cvq3JTe3BuLLc8gW8tWe8jgGK9 F8WgiV+wHUZr7Szgs/hXyn/Kb6CG4qFa7KvqU41D3nv5KpxhSxjF9JOc7xk+SyQOC6Ef dX/8J6RtKAt+5N1ShFj/WWehH6LqnkvbKXkrySPorA7zNZoIPZnIWsErsrTDR4N/m8cO DzATr/BmWuSG6QJB/tGjjDqufAA6bVgApA1rQqPhmYjznCapn6edBoCCK4lzgE01LPtT EHoRYtvMVKHONdJllWICY121+zQAMrLzD6sa+mnUkn1dJAYc7tQgC5QwqUYIddGAxUwR /SFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=Odhp8aGWTIJk5Vd98qOz4L9rXgM79g+QBIzVjFx9lMAuv0CUzk87zaBS+lJOc0q8vH zH44TQbvmxaMvdX7Mh8FhIP5VR55SBNeW3UW/D+rBOyRjY+ZHquYGnRPc7JMKX2681cS Sl47zkPOVHW5DhfqmK405RIhQYAK5GTUkKTdIzga6o95MXsB167vInkMypw6RqYows8y ++WSHZQzX15gH+h/VgIqWewvLKAW2QtV87/238CjuBHZQrTNyzIBwdUNYpHJtMBAfmSX ZAOvuUqb/JGneY5GlT26oLZYhU1efx6XzwtrCOLZQJIWZxj4DIy+owCgOnRvCk9yH8zX TW4A== X-Gm-Message-State: APjAAAUxeuAYkeNiSTB1cZVcA1+OYL6eX+9alYblV9Nq3EWcVD5BqUMi FOcI4L5uWchN13EEe8moeZg= X-Google-Smtp-Source: APXvYqwga4OsIaHauAmhG+osyPhw8HMrpAIGBiK0NmNh8Kv9TJ2rK2/SwoIBlX/GD+Fc1GjJaDrMaQ== X-Received: by 2002:adf:f48d:: with SMTP id l13mr24041248wro.2.1554938129907; Wed, 10 Apr 2019 16:15:29 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id n6sm8504947wmn.48.2019.04.10.16.15.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Apr 2019 16:15:29 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Neil Armstrong , Kevin Hilman Subject: [PATCH 1/8] dt-bindings: gpu: mali-midgard: Add resets property Date: Thu, 11 Apr 2019 01:25:36 +0200 Message-Id: <20190410232543.13297-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190410232543.13297-1-peron.clem@gmail.com> References: <20190410232543.13297-1-peron.clem@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Neil Armstrong The Amlogic ARM Mali Midgard requires reset controls to power on and software reset the GPU, adds these as optional in the bindings. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..1b1a74129141 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -37,6 +37,20 @@ Optional properties: - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt for details. +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-gxm-mali" + Required properties: + - resets : Should contain phandles of : + + GPU reset line + + GPU APB glue reset line Example for a Mali-T760: From patchwork Wed Apr 10 23:25:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1083674 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qaDn8zJe"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fg5D6BzYz9s55 for ; Thu, 11 Apr 2019 09:16:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726825AbfDJXQK (ORCPT ); Wed, 10 Apr 2019 19:16:10 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:42320 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726026AbfDJXPd (ORCPT ); Wed, 10 Apr 2019 19:15:33 -0400 Received: by mail-wr1-f66.google.com with SMTP id g3so4807519wrx.9; Wed, 10 Apr 2019 16:15:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0qACYbWibCn2NYEQtyoZ/KKRf3EQ91V9nFYFBIMWmRE=; b=qaDn8zJeQZMtdJyivrryOFs3/Rh4tV5pTEHX2ACinGABPsL94hSck0mlvN5XXUdLVO 2QshiSkH+/F8/C2sVTH2iSq29/ulGT5/Hr0tOMQBcUDzY7DHfqDJ/bxn096IQqaza05w xG1ce7D8k67kQA0ddLVhuDerJg9hgksF3+OE0M5Ix62EcHMYic0pZna2iysaAEGS8J7U FtBtOb1lvYaEry1Xj0tAqL+RvBPvcm6qvIzeJzFN7f7OKnQFxlD7mcTaM5DLDwjFhZM+ 3YR6jgEC1ry9ZNBgOrn2in5pIa9/Rsfi50i0Ym0C/FVts+Nm24Zwfe+GZpN3GrEZ3A5Y lqtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0qACYbWibCn2NYEQtyoZ/KKRf3EQ91V9nFYFBIMWmRE=; b=qgI4UWxFeGSUoXuTA/Ian1YKwAR7nlVPFuIydiiZUpKOUpB52sQNDAi6/TUPFCH7aU Ud0c3DRneRqD2unkRZSZjM/+K5yy42BL85d7xlBG3zRdmCRNKS/WLugzSPq2LOttX3bt 9RxvsZaW9vgfZs5JZFSrf1i036PC17S7FZ/+/cAPzvsQxPJ60OSiGlvsnFeodLhcVAgD qpO5w/pim9DTkf96KlrcCswG2QeraiGltRiK9Kwr+nKaY1gtqOfWMPQVIcbLcbMkvhB6 +AHeBFV48+p6SbTYj3SUiduLpvREyMmJAmo00BVfckpL2/eZL7K465fkM4btivWu7pb8 UJrw== X-Gm-Message-State: APjAAAViBXFPd+4bBgqTcmwFN94lGBw4Cgzk4B9D/A0SXqVNDsDQ4PUZ 2r49+dsgkO4VL27GvxFSNRc= X-Google-Smtp-Source: APXvYqyBZJPAanBgPDdnRGF5zfKp/yROBhDxSLVw7mZSsuMmbwIMSl2mOOMQa9n0FC87k3dd1GJHVQ== X-Received: by 2002:a5d:530e:: with SMTP id e14mr26166582wrv.18.1554938131542; Wed, 10 Apr 2019 16:15:31 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id n6sm8504947wmn.48.2019.04.10.16.15.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Apr 2019 16:15:30 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH 2/8] dt-bindings: gpu: add bus clock for Mali Midgard GPUs Date: Thu, 11 Apr 2019 01:25:37 +0200 Message-Id: <20190410232543.13297-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190410232543.13297-1-peron.clem@gmail.com> References: <20190410232543.13297-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. + * core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) + * bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. From patchwork Wed Apr 10 23:25:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1083672 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sIlC+CZQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fg555bFMz9s47 for ; Thu, 11 Apr 2019 09:16:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726882AbfDJXQA (ORCPT ); Wed, 10 Apr 2019 19:16:00 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:37576 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726825AbfDJXPe (ORCPT ); Wed, 10 Apr 2019 19:15:34 -0400 Received: by mail-wr1-f66.google.com with SMTP id w10so4844592wrm.4; Wed, 10 Apr 2019 16:15:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kq8Fk6m07P6jzWZ9olFEh1l8VyZCS3V+gmVAUG9Nqhs=; b=sIlC+CZQDLmSAHBjWktNS6GjvQQK+LNh2Dgq4eBoN54cK8kNs3GNfX9w0OFMK8Vgx/ 88kNsVYUoaI1ue4521+OfDimpL74RyzscB3xBDfYWEYYSZ7B0THGuwuV1pRKXScxtVeE ihtGhEaD6A9FHvFmFC5iuuVmXsbvkELR9nXUFA9c2dLd2QtkcR8XIT+W7y8UbEnMXihr i18in6xUY6D7ptZP36+LDhX8ffjT128SAqN4o1EUNd12m+RTttl8/GprNDhCfsvhtE3k fI6YbiPUbEWutFSY1pPGu0+cPFUFJaV1d7JHGtX+tKnC01WIwpE8EEM4iABBAbgo1ECi YpLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kq8Fk6m07P6jzWZ9olFEh1l8VyZCS3V+gmVAUG9Nqhs=; b=Y4LsUjcDHwbARjPrZhF/InjXt/qHA6hFGpIK+QM+apHZ024rW8HoFJe54n9LGQFj8h +OGjOU0V3zYQupGX2pj9XNjJseM+G70GhdkqrxE32IVtIUYIfxRIYOXLUjX8GCZNlzka lUa9IINXlUMvQRgi9HPc/WX/eyIQxu36qa18TRxxpOmB4Yi84UYCTji9WVxTLBo0DCuK IJ3w4G+LQHg6+6leFsMAPuZrgYWJKAzAy+NbXiDW0TlKf5EwxeF6QF/rh5KkvufB64aH Cwcqo7oxJQnKFqgIKvnomqFzWCy8iz1j3rwxSitrG/eC0XPx1ldtpnFJ5MrNMZjTrVnP Bkjg== X-Gm-Message-State: APjAAAUAmAyJ+En5f29gL2fkrH2+sk3Vh5WeZ7AhqtWfZYYV45CnklYa Nb92Y0qrTllfxc0yXj4IexA= X-Google-Smtp-Source: APXvYqy1mP74mIs9gFl+OL7J5jVXFMmS7M1TKpkjWocGf/mK4U0ERj4+bBEPadv2HHx/F6iWPL17Ng== X-Received: by 2002:adf:fa86:: with SMTP id h6mr27837901wrr.67.1554938132715; Wed, 10 Apr 2019 16:15:32 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id n6sm8504947wmn.48.2019.04.10.16.15.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Apr 2019 16:15:31 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH 3/8] dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible Date: Thu, 11 Apr 2019 01:25:38 +0200 Message-Id: <20190410232543.13297-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190410232543.13297-1-peron.clem@gmail.com> References: <20190410232543.13297-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..9e71146b5c8a 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: + + "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,14 @@ Vendor-specific bindings ------------------------ The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - resets: Should contain phandle of : + + GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of :