From patchwork Mon Apr 8 17:02:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1081288 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Mue1nlEl"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44dGvX0Zrpz9sPY for ; Tue, 9 Apr 2019 03:03:04 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B7496C21E0D; Mon, 8 Apr 2019 17:02:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D0EA7C21DF8; Mon, 8 Apr 2019 17:02:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E9E78C21DD4; Mon, 8 Apr 2019 17:02:29 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 3C655C21D4A for ; Mon, 8 Apr 2019 17:02:29 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x38H2LOx030668; Mon, 8 Apr 2019 12:02:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1554742941; bh=sX5oW9VdSedeVz8PPRlCjxmSBUys1yb+kfEA2tFPcLs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Mue1nlElsQRnsOVgwiSlVthPXLJLxpzrCzLIE2xYAKDDYy76eQroqL/bkCWl5dPnH Q/ydx6w2xStILY5Kk1x8L/sSfbW4+vUpBxYrEKO9sAy+drGx45TSIgYwFcokg0jc5W +OcoRDaUGwEyV67dVQzTBO7B3fbs43IxnHU5NO8M= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x38H2LBF027970 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Apr 2019 12:02:21 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 8 Apr 2019 12:02:20 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 8 Apr 2019 12:02:20 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x38H2F4T086673; Mon, 8 Apr 2019 12:02:18 -0500 From: Vignesh Raghavendra To: Albert Aribaud , Lokesh Vutla , Tom Rini Date: Mon, 8 Apr 2019 22:32:59 +0530 Message-ID: <20190408170300.20159-2-vigneshr@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190408170300.20159-1-vigneshr@ti.com> References: <20190408170300.20159-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/2] arch: armv8: Provide a way to disable cache maintenance ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache maintenance operations being done to support non-coherent platforms causes issues. For example, here is how U-Boot prepares/handles a buffer to receive data from a device (DMA Write). This may vary slightly depending on the driver framework: Start DMA to write to destination buffer Wait for DMA to be done (dma_receive()/dma_memcpy()) Invalidate destination buffer (invalidate_dcache_range()) Read from destination buffer The invalidate after the DMA is needed in order to read latest data from memory that’s updated by DMA write. Also, in case random prefetch has pulled in buffer data during the “wait for DMA” before the DMA has written to it. This works well for non-coherent architectures. In case of coherent architecture with L3 cache, DMA write would directly update L3 cache contents (assuming cacheline is present in L3) without updating the DDR memory. So invalidate after “wait for DMA” in above sequence would discard latest data and read will cause stale data to be fetched from DDR. Therefore invalidate after “wait for DMA” is not always correct on coherent architecture. Therefore, provide a Kconfig option to disable cache maintenance ops on coherent architectures. This has added benefit of improving the performance of DMA transfers as we no longer need to invalidate/flush individual cache lines(especially for buffer thats several KBs in size). In order to facilitate use of same Kconfig across different architecture, I have added the symbol to top level arch/Kconfig file. Patch currently disables cache maintenance ops for arm64 only. Signed-off-by: Vignesh Raghavendra --- Changes since RFC: Rename config option to SYS_DISABLE_DCACHE_OPS arch/Kconfig | 9 +++++++++ arch/arm/cpu/armv8/cache_v8.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index 2f3d07c13a18..760023b19a81 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -227,6 +227,15 @@ config SYS_CONFIG_NAME The header file include/configs/.h should be included from include/config.h. +config SYS_DISABLE_DCACHE_OPS + bool + help + This option disables dcache flush and dcache invalidation + operations. For example, on coherent systems where cache + operatios are not required, enable this option to avoid them. + Note that, its up to the individual architectures to implement + this functionality. + source "arch/arc/Kconfig" source "arch/arm/Kconfig" source "arch/m68k/Kconfig" diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 038405173eb1..0febdc0f6090 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -417,6 +417,7 @@ __weak void mmu_setup(void) set_sctlr(get_sctlr() | CR_M); } +#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS /* * Performs a invalidation of the entire data cache at all levels */ @@ -458,6 +459,23 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { __asm_flush_dcache_range(start, stop); } +#else +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} +#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */ void dcache_enable(void) { From patchwork Mon Apr 8 17:03:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1081289 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="fApcwhoS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44dGw74TZpz9sPY for ; Tue, 9 Apr 2019 03:03:35 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 4C401C21DED; Mon, 8 Apr 2019 17:03:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5B49FC21E0D; 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Mon, 8 Apr 2019 12:02:23 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 8 Apr 2019 12:02:23 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 8 Apr 2019 12:02:23 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x38H2F4U086673; Mon, 8 Apr 2019 12:02:21 -0500 From: Vignesh Raghavendra To: Albert Aribaud , Lokesh Vutla , Tom Rini Date: Mon, 8 Apr 2019 22:33:00 +0530 Message-ID: <20190408170300.20159-3-vigneshr@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190408170300.20159-1-vigneshr@ti.com> References: <20190408170300.20159-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/2] board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" AM654 SoC is IO coherent wrt A53 cores, therefore enable SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra --- Changes since RFC: Rename config option to SYS_DISABLE_DCACHE_OPS board/ti/am65x/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index d4b36dbb42f3..98172c28f5d3 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM bool "TI K3 based AM654 EVM running on A53" select ARM64 select SOC_K3_AM6 + select SYS_DISABLE_DCACHE_OPS config TARGET_AM654_R5_EVM bool "TI K3 based AM654 EVM running on R5"