From patchwork Thu Apr 4 05:09:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1076798 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="j4VCF7jN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44ZWGW6g9Vz9sRW for ; Thu, 4 Apr 2019 16:09:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbfDDFJz (ORCPT ); Thu, 4 Apr 2019 01:09:55 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:38777 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbfDDFJx (ORCPT ); Thu, 4 Apr 2019 01:09:53 -0400 Received: by mail-pl1-f194.google.com with SMTP id g37so545693plb.5 for ; Wed, 03 Apr 2019 22:09:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fMDysyCfwc+hqRyd1PaEzIvcoRjPHOAd89SSQWs92AE=; b=j4VCF7jNaQuAIxsT208+FINDEMJxnPuSDb2EXPaui8Zl+KIldPJ1m+9v5OSffLiBkJ DFwz0eOr11NO5R96lmrYaqbN/6hoXyDFZYi/lyg4DVBVvFHviraL9nY3nEUt7HtS6Hex 40wdw1A1hfeChUp4PqbtD8tmurgivN0Tb8Dyh8tYjMtTno8XkKJjBHudK+XAqlw/I6uf IhORxDw//DYuN4yngj92UaaRGEFH0MQ7PBTFz26MueqwbPP78cIVO3XdYVQ3DzOXh9LK 5+rbh+8uB1jcA6LxPCTniS16BqxP4nQ35Rw7EUSo19I1LsheNDhQy391LHVTYwRpRmL7 rUxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fMDysyCfwc+hqRyd1PaEzIvcoRjPHOAd89SSQWs92AE=; b=WMhctBptSKB1F3DvEmDMb3DuUi5CghZkBOBATYnbMKy1PIRnxSyrlZE2NwWviMKKJ7 hZNu4miNLrGutMx2QmRqW/bOYPDvKFRg++pHCUzcEuc8jaH/eGEI1hP/VIcBAdgYzAUC C5iBPdx6k2dQpw6eWs/EezQmxLWpV1BiC7jbYBQ8FDS/VIFii8rLa5WknnFVIkj+t6h6 ERjeDGzlWKizznGCveVdX2d7FCk4BIbE3BWgiR1YhPDGEdHV5rkA1VH3XYmBX3gedrls QCKyxwfhLWb5BvQf6pjUBW1WOditswedkqQfjVmzJ3WNY2uIsHH6F6U5jdW0YVkkLQZp 28sw== X-Gm-Message-State: APjAAAUoB5+JokCPslRInrUsLqdlocy2Sj5Ju0wh6RQDTZUbjc7OOQmO gtIo5oq7XeoLXd/v4AOrqeLPBy0bzLg= X-Google-Smtp-Source: APXvYqweqWp+d84ZI4CgIWMi08hFs+z3ywkPgY2e32VyE2H1v6PGuoevKNOm06jJRMRiTxlOPleR+Q== X-Received: by 2002:a17:902:54f:: with SMTP id 73mr4154967plf.210.1554354592375; Wed, 03 Apr 2019 22:09:52 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id a129sm50589089pfa.152.2019.04.03.22.09.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:09:51 -0700 (PDT) From: Niklas Cassel To: Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Mark Rutland , Andy Gross , David Brown , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, Sricharan R , Niklas Cassel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/9] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Date: Thu, 4 Apr 2019 07:09:23 +0200 Message-Id: <20190404050931.9812-3-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sricharan R The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse. Signed-off-by: Sricharan R Signed-off-by: Niklas Cassel --- ...ryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 16 +-- drivers/cpufreq/Kconfig.arm | 4 +- drivers/cpufreq/Makefile | 2 +- ...om-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 +++++++++++------- 4 files changed, 85 insertions(+), 61 deletions(-) rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (97%) rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (69%) diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt similarity index 97% rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index c2127b96805a..f4a7123730c3 100644 --- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -1,13 +1,13 @@ -Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings +Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings =================================== -In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 -that have KRYO processors, the CPU ferequencies subset and voltage value -of each OPP varies based on the silicon variant in use. +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, +the CPU frequencies subset and voltage value of each OPP varies based on +the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. -The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC +The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. @@ -19,7 +19,7 @@ In 'cpus' nodes: In 'operating-points-v2' table: - compatible: Should be - - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. + - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996. - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage @@ -127,7 +127,7 @@ Example 1: }; cluster0_opp: opp_table0 { - compatible = "operating-points-v2-kryo-cpu"; + compatible = "operating-points-v2-qcom-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; @@ -338,7 +338,7 @@ Example 1: }; cluster1_opp: opp_table1 { - compatible = "operating-points-v2-kryo-cpu"; + compatible = "operating-points-v2-qcom-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 179a1d302f48..2e4aefa0f34d 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -110,8 +110,8 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS -config ARM_QCOM_CPUFREQ_KRYO - tristate "Qualcomm Kryo based CPUFreq" +config ARM_QCOM_CPUFREQ_NVMEM + tristate "Qualcomm nvmem based CPUFreq" depends on ARM64 depends on QCOM_QFPROM depends on QCOM_SMEM diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 689b26c6f949..8e83fd73bd2d 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -63,7 +63,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o -obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c similarity index 69% rename from drivers/cpufreq/qcom-cpufreq-kryo.c rename to drivers/cpufreq/qcom-cpufreq-nvmem.c index dd64dcf89c74..652a1de2a5d4 100644 --- a/drivers/cpufreq/qcom-cpufreq-kryo.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -9,7 +9,7 @@ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. - * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC + * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC * to provide the OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -42,9 +43,9 @@ enum _msm8996_version { NUM_OF_MSM8996_VERSIONS, }; -static struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev; +static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; -static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) +static enum _msm8996_version qcom_cpufreq_get_msm_id(void) { size_t len; u32 *msm_id; @@ -73,34 +74,68 @@ static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) return version; } -static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) +static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + u32 *versions) { - struct opp_table **opp_tables; + size_t len; + u8 *speedbin; enum _msm8996_version msm8996_version; + + msm8996_version = qcom_cpufreq_get_msm_id(); + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { + dev_err(cpu_dev, "Not Snapdragon 820/821!"); + return -ENODEV; + } + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + switch (msm8996_version) { + case MSM8996_V3: + *versions = 1 << (unsigned int)(*speedbin); + break; + case MSM8996_SG: + *versions = 1 << ((unsigned int)(*speedbin) + 4); + break; + default: + BUG(); + break; + } + + kfree(speedbin); + return 0; +} + +static int qcom_cpufreq_probe(struct platform_device *pdev) +{ + struct opp_table **opp_tables; + int (*get_version)(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + u32 *versions); struct nvmem_cell *speedbin_nvmem; struct device_node *np; struct device *cpu_dev; unsigned cpu; - u8 *speedbin; u32 versions; - size_t len; + const struct of_device_id *match; int ret; cpu_dev = get_cpu_device(0); if (!cpu_dev) return -ENODEV; - msm8996_version = qcom_cpufreq_kryo_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); + match = pdev->dev.platform_data; + get_version = match->data; + if (!get_version) return -ENODEV; - } np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu"); if (!ret) { of_node_put(np); return -ENOENT; @@ -115,23 +150,10 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) return PTR_ERR(speedbin_nvmem); } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); + ret = get_version(cpu_dev, speedbin_nvmem, &versions); nvmem_cell_put(speedbin_nvmem); - if (IS_ERR(speedbin)) - return PTR_ERR(speedbin); - - switch (msm8996_version) { - case MSM8996_V3: - versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: - versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); - break; - } - kfree(speedbin); + if (ret) + return ret; opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); if (!opp_tables) @@ -174,7 +196,7 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) return ret; } -static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) +static int qcom_cpufreq_remove(struct platform_device *pdev) { struct opp_table **opp_tables = platform_get_drvdata(pdev); unsigned int cpu; @@ -189,18 +211,20 @@ static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) return 0; } -static struct platform_driver qcom_cpufreq_kryo_driver = { - .probe = qcom_cpufreq_kryo_probe, - .remove = qcom_cpufreq_kryo_remove, +static struct platform_driver qcom_cpufreq_driver = { + .probe = qcom_cpufreq_probe, + .remove = qcom_cpufreq_remove, .driver = { - .name = "qcom-cpufreq-kryo", + .name = "qcom-cpufreq", }, }; -static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { - { .compatible = "qcom,apq8096", }, - { .compatible = "qcom,msm8996", }, - {} +static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { + { .compatible = "qcom,apq8096", + .data = qcom_cpufreq_kryo_name_version }, + { .compatible = "qcom,msm8996", + .data = qcom_cpufreq_kryo_name_version }, + {}, }; /* @@ -209,7 +233,7 @@ static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { * which may be defered as well. The init here is only registering * the driver and the platform device. */ -static int __init qcom_cpufreq_kryo_init(void) +static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; @@ -218,32 +242,32 @@ static int __init qcom_cpufreq_kryo_init(void) if (!np) return -ENODEV; - match = of_match_node(qcom_cpufreq_kryo_match_list, np); + match = of_match_node(qcom_cpufreq_match_list, np); of_node_put(np); if (!match) return -ENODEV; - ret = platform_driver_register(&qcom_cpufreq_kryo_driver); + ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; - kryo_cpufreq_pdev = platform_device_register_simple( - "qcom-cpufreq-kryo", -1, NULL, 0); - ret = PTR_ERR_OR_ZERO(kryo_cpufreq_pdev); + cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq", + -1, match, sizeof(*match)); + ret = PTR_ERR_OR_ZERO(cpufreq_pdev); if (0 == ret) return 0; - platform_driver_unregister(&qcom_cpufreq_kryo_driver); + platform_driver_unregister(&qcom_cpufreq_driver); return ret; } -module_init(qcom_cpufreq_kryo_init); +module_init(qcom_cpufreq_init); -static void __exit qcom_cpufreq_kryo_exit(void) +static void __exit qcom_cpufreq_exit(void) { - platform_device_unregister(kryo_cpufreq_pdev); - platform_driver_unregister(&qcom_cpufreq_kryo_driver); + platform_device_unregister(cpufreq_pdev); + platform_driver_unregister(&qcom_cpufreq_driver); } -module_exit(qcom_cpufreq_kryo_exit); +module_exit(qcom_cpufreq_exit); -MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver"); +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); MODULE_LICENSE("GPL v2"); From patchwork Thu Apr 4 05:09:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1076799 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="OQusTV+s"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44ZWHV4vJfz9sRW for ; Thu, 4 Apr 2019 16:10:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727025AbfDDFKl (ORCPT ); Thu, 4 Apr 2019 01:10:41 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:38602 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726222AbfDDFKl (ORCPT ); Thu, 4 Apr 2019 01:10:41 -0400 Received: by mail-pf1-f196.google.com with SMTP id 10so735696pfo.5 for ; Wed, 03 Apr 2019 22:10:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5f+kkMUgvOOpOd6cTF9Ie+6FOr6453kj1E1ya/v5Za8=; b=OQusTV+sLzBgbuQim/aJBTk/xjcBPTqYlFT9scR6O8fYzA0i29sdhhV5Jnxg81dPHL MwAFl+bs31OrLE9iQXLisbdttm0uhX7lBVJOLlI3joGVjmPJ6uPi0qF4Tt8gAR7JbWdZ SvVAnPMZu0ZxSSXF9Ap7xv/YSNby0tIJIqwSeSjlSl6zskXvNpgv5CAofOoQf3BRztZ+ y+LYNuu4+wmQ32CfLWWUzCnFzLJPWclgKOPHXyxiwJitkTI8+9f8jv37IfGfhgQLMUIV k+yDCnbs4xXT2c2ttyqaycOFf5Kt5efXpoxaXHPnnFSUnBRN+2LZ034sjgPgD3U0wydF FwOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5f+kkMUgvOOpOd6cTF9Ie+6FOr6453kj1E1ya/v5Za8=; b=imOVweu1Xk3LvfyGV9qskingOubD+4Cud/yrKO+hy1FGgRnMezwBGZPNQ7Dc4+NR8y V4BKkO8FzjbBewpd2HG2er6ZwK4VS8VeIVqSml6lr5+TptR4Z6EvI2PbdZUFd9i5AQTw jpauQmx7ybnnFvnK6Ej3dyWF9tRFnzC6pkGxeW2w8nP8zKEpi1q+2cRn/+x/+B27XJnA UIFQCdJIMhbrnjjcBGiX5q57MJ7iXfcHXpaJYp7HA64hzDDGXkm2rlnv5eQLMp78H2Jb NCPB86yC7FUDHU9ksOR2QXAwIVj4xYP6AGEVchULyZOQ6k4W0sxdMaQ+iVe3dG1iHVzO Of+w== X-Gm-Message-State: APjAAAVcgHAnsUAK7ra58c06775TkjwlwM7CMBvEAJVjzXiaP4i8f30n Ipt0xJChvbRbws4My7bSdk1SmA== X-Google-Smtp-Source: APXvYqw74PUpVJSwVuvWlGLT47IEyHp+tLAw/NzY+y0YXokm/P1+rW7kGVyLoErD4bt5pU5wxB0X0A== X-Received: by 2002:a63:1064:: with SMTP id 36mr3772475pgq.155.1554354640554; Wed, 03 Apr 2019 22:10:40 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id g64sm43254361pfg.13.2019.04.03.22.10.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:10:40 -0700 (PDT) From: Niklas Cassel To: Andy Gross , David Brown , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, Niklas Cassel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 6/9] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Date: Thu, 4 Apr 2019 07:09:27 +0200 Message-Id: <20190404050931.9812-7-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add qcom-opp bindings with properties needed for Core Power Reduction (CPR). CPR is included in a great variety of Qualcomm SoC, e.g. msm8916 and msm8996, and was first introduced in msm8974. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- .../devicetree/bindings/opp/qcom-opp.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt new file mode 100644 index 000000000000..d24280467db7 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -0,0 +1,24 @@ +Qualcomm OPP bindings to describe OPP nodes + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-qcom-level" + +* OPP Node + +Optional properties: +- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. Even + though a power domain doesn't need a opp-hz, there can be devices in the + power domain that need to know the highest supported frequency for each + corner/level (e.g. CPR), in order to properly initialize the hardware. + +- qcom,opp-fuse-level: A positive value representing the fuse corner/level + associated with this OPP node. Sometimes several corners/levels shares + a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, + min uV, and max uV. From patchwork Thu Apr 4 05:09:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1076800 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="TVrlYzkJ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44ZWHY2BFRz9sSZ for ; Thu, 4 Apr 2019 16:10:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727057AbfDDFKs (ORCPT ); Thu, 4 Apr 2019 01:10:48 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34201 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727053AbfDDFKs (ORCPT ); Thu, 4 Apr 2019 01:10:48 -0400 Received: by mail-pf1-f195.google.com with SMTP id b3so746881pfd.1 for ; Wed, 03 Apr 2019 22:10:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KklAnXYLBcaWUwOXv3w+NPnCSqij3vKIBVWvRjd2T1M=; b=TVrlYzkJah4xdZ0w8EvrnSm/BK2kbCUs+gYrh4qHXuTB+9XfnOKDUijzhXIOhYcCQ1 lMWLSiwQm+HBmQ8e4X8RqpPvj65Nem5N7MMVM86i766VY6p6IXLsPIDlRbHoOoXhjrkM i41Ogs62ITdcsCP4H3olAyjjOUko92YbM/gLAPKf3PBVt/OaCvR34FNNUfU/GGNzxrDt 4dK87LDFQXJLL/EefUGM7xmBQ9sKFFy/Np27g9F+KAJFqgzDyy3t5QGS+0VMhXbPKQwv Dkb9xcd4wT7vQL5n7o1j4Ra+ue6z78MoWYjjfcBc4E1tnEXZ3IG9Y1v+bcdpW/aD3CTf rdPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KklAnXYLBcaWUwOXv3w+NPnCSqij3vKIBVWvRjd2T1M=; b=GmTIXdXfM4Nzr4bP9mHb0bUDN5o+gHMQ7WBe1zNSfzTlniQD4R7MftpSzLEbty8JWJ lP+K3XgHJvSCJgYqB10SI+o5tB28UqApbIJWA7NaGF2DZ8z/rtjwKCBfuKT22xru2ObJ ntmpdPVu2xFkjuCupsVB1kaOqBpOR/3qXEGQYKGL4oSQ7ibuFyJN60JbO0HIxePfp8H5 86Ri6sBCkfFNhzpOMo6RPyYsnM6mrPPV9HGzOcw+D6t47wQw5j9/Dw/VZHuePFX+kGOa CvCN5/RO12YZdJz/AB2thGSDInIGlRWHzjZuB6KlOWN86Q4eYmPZ5Zgx+7Uh3qkm7St4 uzZQ== X-Gm-Message-State: APjAAAWwoNr+4jyuyDKzBxFqm7kndHDcFa0MTuVqqnRPe2/oqAZP2lh8 40SZggRZ4SfzWqCVT4HUpXZjlg== X-Google-Smtp-Source: APXvYqy17XvZpOsXAVU3uU50LFA03fh5j3uiMNXPtk8QswXoP6g8HpJA/G8U3H2/zvSa2I3B9C0CYg== X-Received: by 2002:a62:1318:: with SMTP id b24mr3620039pfj.201.1554354647500; Wed, 03 Apr 2019 22:10:47 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id g64sm43254361pfg.13.2019.04.03.22.10.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:10:46 -0700 (PDT) From: Niklas Cassel To: Rob Herring , Mark Rutland , Jorge Ramirez-Ortiz , Niklas Cassel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 7/9] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Date: Thu, 4 Apr 2019 07:09:28 +0200 Message-Id: <20190404050931.9812-8-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- .../bindings/power/avs/qcom,cpr.txt | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt new file mode 100644 index 000000000000..541c9b31cd3b --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -0,0 +1,119 @@ +QCOM CPR (Core Power Reduction) + +CPR (Core Power Reduction) is a technology to reduce core power on a CPU +or other device. Each OPP of a device corresponds to a "corner" that has +a range of valid voltages for a particular frequency. While the device is +running at a particular frequency, CPR monitors dynamic factors such as +temperature, etc. and suggests adjustments to the voltage to save power +and meet silicon characteristic requirements. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,cpr" + +- reg: + Usage: required + Value type: + Definition: base address and size of the rbcpr register region + +- interrupts: + Usage: required + Value type: + Definition: list of three interrupts in order of irq0, irq1, irq2 + +- acc-syscon: + Usage: optional + Value type: + Definition: phandle to syscon for writing ACC settings + +- nvmem: + Usage: required + Value type: + Definition: phandle to nvmem provider containing efuse settings + +- nvmem-names: + Usage: required + Value type: + Definition: must be "qfprom" + +vdd-mx-supply = <&pm8916_l3>; + +- qcom,cpr-ref-clk: + Usage: required + Value type: + Definition: rate of reference clock in kHz + +- qcom,cpr-timer-delay-us: + Usage: required + Value type: + Definition: delay in uS for the timer interval + +- qcom,cpr-timer-cons-up: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing an up + interrupt + +- qcom,cpr-timer-cons-down: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing a down + interrupt + +- qcom,cpr-up-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping up + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrdownt when error_steps + is greater than it when stepping down + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: Idle clock cycles ring oscillator can be in + +- qcom,cpr-gcnt-us: + Usage: required + Value type: + Definition: The time for gate count in uS + +- qcom,vdd-apc-step-up-limit: + Usage: required + Value type: + Definition: Limit of vdd-apc-supply steps for scaling up + +- qcom,vdd-apc-step-down-limit: + Usage: required + Value type: + Definition: Limit of vdd-apc-supply steps for scaling down + +Example: + + avs@b018000 { + compatible = "qcom,cpr"; + reg = <0xb018000 0x1000>; + interrupts = <0 15 1>, <0 16 1>, <0 17 1>; + vdd-mx-supply = <&pm8916_l3>; + acc-syscon = <&tcsr>; + nvmem = <&qfprom>; + nvmem-names = "qfprom"; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay-us = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-up-threshold = <0>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-us = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + };