@@ -90,9 +90,6 @@ struct mlxbf_gige {
dma_addr_t rx_cqe_base_dma;
u16 tx_pi;
u16 prev_tx_ci;
- u64 error_intr_count;
- u64 rx_intr_count;
- u64 llu_plu_intr_count;
struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ];
struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ];
int error_irq;
@@ -24,11 +24,9 @@ static void mlxbf_gige_get_regs(struct net_device *netdev,
regs->version = MLXBF_GIGE_REGS_VERSION;
/* Read entire MMIO register space and store results
- * into the provided buffer. Each 64-bit word is converted
- * to big-endian to make the output more readable.
- *
- * NOTE: by design, a read to an offset without an existing
- * register will be acknowledged and return zero.
+ * into the provided buffer. By design, a read to an
+ * offset without an existing register will be
+ * acknowledged and return zero.
*/
memcpy_fromio(p, priv->base, MLXBF_GIGE_MMIO_REG_SZ);
}
@@ -17,8 +17,6 @@ static irqreturn_t mlxbf_gige_error_intr(int irq, void *dev_id)
priv = dev_id;
- priv->error_intr_count++;
-
int_status = readq(priv->base + MLXBF_GIGE_INT_STATUS);
if (int_status & MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR)
@@ -75,8 +73,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id)
priv = dev_id;
- priv->rx_intr_count++;
-
/* NOTE: GigE silicon automatically disables "packet rx" interrupt by
* setting MLXBF_GIGE_INT_MASK bit0 upon triggering the interrupt
* to the ARM cores. Software needs to re-enable "packet rx"
@@ -90,11 +86,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id)
static irqreturn_t mlxbf_gige_llu_plu_intr(int irq, void *dev_id)
{
- struct mlxbf_gige *priv;
-
- priv = dev_id;
- priv->llu_plu_intr_count++;
-
return IRQ_HANDLED;
}