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[v1,1/1] UBUNTU: SAUCE: [SRU][J:linux-bluefield] mmc:sdhci-of-dwcmshc: Add hw_reset() support for BlueField-3 SoC

Message ID 8b17c2f11409a4c53b604a01528bec3686952196.1720719340.git.limings@nvidia.com
State New
Headers show
Series UBUNTU: SAUCE: [SRU][J:linux-bluefield] mmc:sdhci-of-dwcmshc: Add hw_reset() support for BlueField-3 SoC | expand

Commit Message

Liming Sun July 11, 2024, 5:48 p.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/2072786

The eMMC RST_N register is implemented as secure register on
the BlueField-3 SoC and controlled by TF-A. This commit adds the
hw_reset() support which sends an SMC call to TF-A for the eMMC
HW reset.

Reviewed-by: David Thompson <davthompson@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 4d19d4ec01f8..23c7f5d28837 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -8,6 +8,7 @@ 
  */
 
 #include <linux/acpi.h>
+#include <linux/arm-smccc.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/iopoll.h>
@@ -22,6 +23,9 @@ 
 
 #include "sdhci-pltfm.h"
 
+/* SMC call for RST_N */
+#define BLUEFIELD_SMC_SET_EMMC_RST_N	0x82000007
+
 #define SDHCI_DWCMSHC_ARG2_STUFF	GENMASK(31, 16)
 
 /* DWCMSHC specific Mode Select value */
@@ -274,6 +278,18 @@  static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
 	sdhci_reset(host, mask);
 }
 
+#ifdef CONFIG_ACPI
+static void dwcmshc_bf3_hw_reset(struct sdhci_host *host)
+{
+	struct arm_smccc_res res = { 0 };
+
+	arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	if (res.a0)
+		pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc));
+}
+#endif
+
 static const struct sdhci_ops sdhci_dwcmshc_ops = {
 	.set_clock		= sdhci_set_clock,
 	.set_bus_width		= sdhci_set_bus_width,
@@ -299,8 +315,18 @@  static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
 };
 
 #ifdef CONFIG_ACPI
+static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = {
+	.set_clock		= sdhci_set_clock,
+	.set_bus_width		= sdhci_set_bus_width,
+	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
+	.get_max_clock		= dwcmshc_get_max_clock,
+	.reset			= sdhci_reset,
+	.adma_write_desc	= dwcmshc_adma_write_desc,
+	.hw_reset		= dwcmshc_bf3_hw_reset,
+};
+
 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
-	.ops = &sdhci_dwcmshc_ops,
+	.ops = &sdhci_dwcmshc_bf3_ops,
 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |