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[SRU,J:linux-bluefield,v1,1/1] UBUNTU: SAUCE: sdhci-of-dwcmshc-bf3: Enable SDHCI_QUIRK_BROKEN_TIMEOUT_VAL

Message ID 40bb2bd3e51e6c642a62eda88a268a344755a1b4.1697654797.git.limings@nvidia.com
State New
Headers show
Series UBUNTU: SAUCE: sdhci-of-dwcmshc-bf3: Enable SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | expand

Commit Message

Liming Sun Oct. 18, 2023, 6:54 p.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/2039325

This commit enables SDHCI_QUIRK_BROKEN_TIMEOUT_VAL to fix the
intermittent eMMC timeout issue. eMMC has two timeout, one is in
the controller and one is configured in OS. Previously, both are
calculated on top of configuration read from eMMC CSD register and
clock setting. With the quirk setting, controller timeout value
0xe (max value) will be used which is the same as UEFI does. The OS
timeout will be set to 10 seconds accordingly.

Signed-off-by: Liming Sun <limings@nvidia.com>
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 44fd58014b7f..188c5ae7efc5 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -316,7 +316,8 @@  static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
 #ifdef CONFIG_ACPI
 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
 	.ops = &sdhci_dwcmshc_ops,
-	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 		   SDHCI_QUIRK2_ACMD23_BROKEN,
 };