From patchwork Wed Oct 2 19:52:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Reed X-Patchwork-Id: 1992162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com (client-ip=185.125.189.65; helo=lists.ubuntu.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=patchwork.ozlabs.org) Received: from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XJlq55RVsz1xtn for ; Thu, 3 Oct 2024 05:53:20 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=lists.ubuntu.com) by lists.ubuntu.com with esmtp (Exim 4.86_2) (envelope-from ) id 1sw5PG-0002tP-N4; Wed, 02 Oct 2024 19:53:06 +0000 Received: from smtp-relay-internal-1.internal ([10.131.114.114] helo=smtp-relay-internal-1.canonical.com) by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1sw5PF-0002oE-2A for kernel-team@lists.ubuntu.com; Wed, 02 Oct 2024 19:53:05 +0000 Received: from mail-oo1-f72.google.com (mail-oo1-f72.google.com [209.85.161.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 9D1423F2E4 for ; Wed, 2 Oct 2024 19:53:04 +0000 (UTC) Received: by mail-oo1-f72.google.com with SMTP id 006d021491bc7-5df92c75f1aso196546eaf.0 for ; Wed, 02 Oct 2024 12:53:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727898783; x=1728503583; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EfQo4rKOnSo28AEKXF1NohJ1qJxVFuPVPvjlP09aPrc=; b=SE7OqtQNq417rXKRP9tiZSvwo+0pwdhPYBCrMfcbs0ZknU4NtsNHLWfqiYyirxvi12 lgPeCnydD7KT0AmKVhAUJ2nlHD3uII30kUGYHvEOjlRq6UkFvq5oO56eTy1k2RCrC6rT 40iIAEEWHRjQ5eb5sWzFe7LFu2cnMtvHfckyy0bOzZH3RmeRWd11Olb7LUx8jJA6dhqO rV5tM/2tWRk11z2/f4QENWAMvIccKJXZ1i3dHQqFgIpoMdQeyE4ZXxvSEh3LgLGGdyD6 q4xsYXGnB7MrfZyQf8RRdSwO6M/r0LXrgdL82KC0jL3btLt2L1ay4Q/O3nwAnfr1YkeC aN8w== X-Gm-Message-State: AOJu0YxR0YM/iFI+sO/XcH1Pv8+OxYw609BIGXjNIaXc5LoeQwmNapca h5k0KEzm2NsCkK05lJ/PdbMFUVUroayxQSLy68H1XB43o1S7SlMLYuxxc3nKZkbbHcwY/SdjydK i9MtgqeBWg8cp9cZPDLq5M2UfCUw078EgHUt4DQN9qJFp+yXOL/m8iyYWym+p72ud5CrdYxqXSD djcWMdGe4uKw== X-Received: by 2002:a05:6820:2716:b0:5e5:c0a0:2b53 with SMTP id 006d021491bc7-5e7b1bf5544mr2545369eaf.0.1727898783079; Wed, 02 Oct 2024 12:53:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVBwAT18J+F5aK18cnEnlJTTl/PIiifMhAwJZBMm3zS7k6fqIixrZTlnkV5bN0N3FtvFH3IA== X-Received: by 2002:a05:6820:2716:b0:5e5:c0a0:2b53 with SMTP id 006d021491bc7-5e7b1bf5544mr2545353eaf.0.1727898782601; Wed, 02 Oct 2024 12:53:02 -0700 (PDT) Received: from localhost ([2600:1700:1d0:5e50:2f4c:f8fc:2036:7a63]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5e770eabe2fsm3465669eaf.38.2024.10.02.12.53.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 12:53:02 -0700 (PDT) From: Michael Reed To: kernel-team@lists.ubuntu.com Subject: [SRU N][PATCH 0/1] Arrow Lake IBECC feature backport request for ubuntu 6.8 Date: Wed, 2 Oct 2024 14:52:59 -0500 Message-Id: <20241002195300.25591-1-michael.reed@canonical.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Michael Reed BugLink: https://bugs.launchpad.net/bugs/2077861 SRU Justification: [Impact] Add Arrow Lake-U/H SoC compute die IDs for EDAC support. [Test Plan] [Fix] According to https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=88150cd9501b9498e377cc4440325267c6921f90, Intel Arrow Lake IBECC(In-Band ECC)) feature is already added in upstream. """"" author Qiuxu Zhuo 2024-06-14 11:03:54 +0800 committer Tony Luck 2024-06-14 08:08:12 -0700 commit 88150cd9501b9498e377cc4440325267c6921f90 (patch) tree fc574a0966af4f31dcc7247ff3fbbdcccffb1089 parent 123b158635505c89ed0d3ef45c5845ff9030a466 (diff) download linux-88150cd9501b9498e377cc4440325267c6921f90.tar.gz EDAC/igen6: Add Intel Arrow Lake-U/H SoCs support Arrow Lake-U/H SoCs share same IBECC registers with Meteor Lake-P SoCs. Add Arrow Lake-U/H SoC compute die IDs for EDAC support. Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Link: https://lore.kernel.org/r/20240614030354.69180-1-qiuxu.zhuo@intel.com Diffstat -rw-r--r-- drivers/edac/igen6_edac.c 8 1 files changed, 8 insertions, 0 deletions """"" [Where problems could occur] [Other Info] https://code.launchpad.net/~mreed8855/ubuntu/+source/linux/+git/noble/+ref/lp_2077861_intel_arrowlake_ibecc Qiuxu Zhuo (1): EDAC/igen6: Add Intel Arrow Lake-U/H SoCs support drivers/edac/igen6_edac.c | 8 ++++++++ 1 file changed, 8 insertions(+) Acked-by: Ivan Hu Acked-by: Chris Chiu diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index cdd8480e736877..c9fc1e64069e33 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -258,6 +258,11 @@ static struct work_struct ecclog_work; #define DID_MTL_P_SKU2 0x7d02 #define DID_MTL_P_SKU3 0x7d14 +/* Compute die IDs for Arrow Lake-UH with IBECC */ +#define DID_ARL_UH_SKU1 0x7d06 +#define DID_ARL_UH_SKU2 0x7d20 +#define DID_ARL_UH_SKU3 0x7d30 + static int get_mchbar(struct pci_dev *pdev, u64 *mchbar) { union { @@ -597,6 +602,9 @@ static const struct pci_device_id igen6_pci_tbl[] = { { PCI_VDEVICE(INTEL, DID_MTL_P_SKU1), (kernel_ulong_t)&mtl_p_cfg }, { PCI_VDEVICE(INTEL, DID_MTL_P_SKU2), (kernel_ulong_t)&mtl_p_cfg }, { PCI_VDEVICE(INTEL, DID_MTL_P_SKU3), (kernel_ulong_t)&mtl_p_cfg }, + { PCI_VDEVICE(INTEL, DID_ARL_UH_SKU1), (kernel_ulong_t)&mtl_p_cfg }, + { PCI_VDEVICE(INTEL, DID_ARL_UH_SKU2), (kernel_ulong_t)&mtl_p_cfg }, + { PCI_VDEVICE(INTEL, DID_ARL_UH_SKU3), (kernel_ulong_t)&mtl_p_cfg }, { }, }; MODULE_DEVICE_TABLE(pci, igen6_pci_tbl);