From patchwork Wed Sep 18 20:51:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Reed X-Patchwork-Id: 1986987 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com (client-ip=185.125.189.65; helo=lists.ubuntu.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=patchwork.ozlabs.org) Received: from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X89nc2FCwz1y2j for ; Thu, 19 Sep 2024 06:52:20 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=lists.ubuntu.com) by lists.ubuntu.com with esmtp (Exim 4.86_2) (envelope-from ) id 1sr1eL-0004EM-3z; Wed, 18 Sep 2024 20:51:45 +0000 Received: from smtp-relay-internal-0.internal ([10.131.114.225] helo=smtp-relay-internal-0.canonical.com) by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1sr1eC-0004BZ-7V for kernel-team@lists.ubuntu.com; Wed, 18 Sep 2024 20:51:36 +0000 Received: from mail-oo1-f69.google.com (mail-oo1-f69.google.com [209.85.161.69]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id F03103F458 for ; Wed, 18 Sep 2024 20:51:35 +0000 (UTC) Received: by mail-oo1-f69.google.com with SMTP id 006d021491bc7-5e56a096565so142686eaf.2 for ; Wed, 18 Sep 2024 13:51:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726692689; x=1727297489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xAdKa6jXZ49LrX6o88zxU5OZ7FzQKu1CMqd2IuxLQTo=; b=V4soORMEdI90jKamt0jI017AaKtIcw3iTWKUQnFXSQ1f1Q0Zw5jskcYwtxAT9gVPG/ ipXBBVIO+IPieQhgDZnz62wjNInAjwUfHV2BMnZEVLb2Kyq2jzonhpopb+YBVPsYb3T7 gRJpcfYA7hqtyXg824RZNkuqAMJvnF3WZ+PaL+1Y+rnYNK2RV1z85p0hGw2IViRPRCuQ Fla7iXLTt1C4A1aDgGSGoM8i4gKFSi42GnKyJHvR0ItVIxR79lSyAuynDE2EKoGFaEnz FEf1WU99wMAAGepevfO2iws5moT+B6M3Aztg6zkFpwAGlgs/sCgGl+mTzoGQx0vRcCBg VPOw== X-Gm-Message-State: AOJu0YyHzAhzKhEZ/hN3v5oSyUOitcqS/JxkRDn19eHenBRYiK4//e/t SHu45cFfXwMXdrlUq6XoW5R1sGUAnLYbqdIzl+EK+90O3uOEv4BH8sws1h4tESSDYy/5h0Qfb/2 4hWktk8rB5Mx7JL78EBurIHLsMz2f2cngYlMDsuDs3m28TRM2BrZk4Lm735m9wBQB15SQeiwlcT NW8oLg8Mmb8cZd X-Received: by 2002:a05:6820:1c98:b0:5e1:de92:6b4c with SMTP id 006d021491bc7-5e20c2790dbmr11787256eaf.1.1726692689564; Wed, 18 Sep 2024 13:51:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEp+wLzVzy2gCxLy3fUCLSA7FOSSuTbwuuUg5hmAKP4dsMwZ0KcbQxaxnY0mgnlv4WX4bLahw== X-Received: by 2002:a05:6820:1c98:b0:5e1:de92:6b4c with SMTP id 006d021491bc7-5e20c2790dbmr11787247eaf.1.1726692689197; Wed, 18 Sep 2024 13:51:29 -0700 (PDT) Received: from localhost ([2600:1700:1d0:5e50:4536:727e:1556:7bf1]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5e5683a6ef9sm786988eaf.34.2024.09.18.13.51.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 13:51:28 -0700 (PDT) From: Michael Reed To: kernel-team@lists.ubuntu.com Subject: [SRU][N][PATCH 8/8] perf/x86/intel/uncore: Support HBM and CXL PMON counters Date: Wed, 18 Sep 2024 15:51:14 -0500 Message-Id: <20240918205114.31083-9-michael.reed@canonical.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918205114.31083-1-michael.reed@canonical.com> References: <20240918205114.31083-1-michael.reed@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Kan Liang BugLink: https://bugs.launchpad.net/bugs/2081079 Unknown uncore PMON types can be found in both SPR and EMR with HBM or CXL. $ls /sys/devices/ | grep type uncore_type_12_16 uncore_type_12_18 uncore_type_12_2 uncore_type_12_4 uncore_type_12_6 uncore_type_12_8 uncore_type_13_17 uncore_type_13_19 uncore_type_13_3 uncore_type_13_5 uncore_type_13_7 uncore_type_13_9 The unknown PMON types are HBM and CXL PMON. Except for the name, the other information regarding the HBM and CXL PMON counters can be retrieved via the discovery table. Add them into the uncores tables for SPR and EMR. The event config registers for all CXL related units are 8-byte apart. Add SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT to specially handle it. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Tested-by: Yunying Sun Link: https://lore.kernel.org/r/20240614134631.1092359-9-kan.liang@linux.intel.com (cherry picked from commit f8a86a9bb5f7e65d8c4405052de062639a8783bb) Signed-off-by: Michael Reed --- arch/x86/events/intel/uncore_snbep.c | 55 +++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index d51d3e6dd2b8..8f23c0247305 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6162,7 +6162,55 @@ static struct intel_uncore_type spr_uncore_mdf = { .name = "mdf", }; -#define UNCORE_SPR_NUM_UNCORE_TYPES 12 +static void spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box) +{ + __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); + intel_generic_uncore_mmio_init_box(box); +} + +static struct intel_uncore_ops spr_uncore_mmio_offs8_ops = { + .init_box = spr_uncore_mmio_offs8_init_box, + .exit_box = uncore_mmio_exit_box, + .disable_box = intel_generic_uncore_mmio_disable_box, + .enable_box = intel_generic_uncore_mmio_enable_box, + .disable_event = intel_generic_uncore_mmio_disable_event, + .enable_event = spr_uncore_mmio_enable_event, + .read_counter = uncore_mmio_read_counter, +}; + +#define SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT() \ + SPR_UNCORE_COMMON_FORMAT(), \ + .ops = &spr_uncore_mmio_offs8_ops + +static struct event_constraint spr_uncore_cxlcm_constraints[] = { + UNCORE_EVENT_CONSTRAINT(0x02, 0x0f), + UNCORE_EVENT_CONSTRAINT(0x05, 0x0f), + UNCORE_EVENT_CONSTRAINT(0x40, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x41, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x42, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x43, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x52, 0xf0), + EVENT_CONSTRAINT_END +}; + +static struct intel_uncore_type spr_uncore_cxlcm = { + SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), + .name = "cxlcm", + .constraints = spr_uncore_cxlcm_constraints, +}; + +static struct intel_uncore_type spr_uncore_cxldp = { + SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), + .name = "cxldp", +}; + +static struct intel_uncore_type spr_uncore_hbm = { + SPR_UNCORE_COMMON_FORMAT(), + .name = "hbm", +}; + +#define UNCORE_SPR_NUM_UNCORE_TYPES 15 #define UNCORE_SPR_CHA 0 #define UNCORE_SPR_IIO 1 #define UNCORE_SPR_IMC 6 @@ -6186,6 +6234,9 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { NULL, NULL, &spr_uncore_mdf, + &spr_uncore_cxlcm, + &spr_uncore_cxldp, + &spr_uncore_hbm, }; /* @@ -6655,7 +6706,7 @@ static struct intel_uncore_type gnr_uncore_b2cmi = { }; static struct intel_uncore_type gnr_uncore_b2cxl = { - SPR_UNCORE_MMIO_COMMON_FORMAT(), + SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), .name = "b2cxl", };