diff mbox series

[SRU,jammy:linux-xilinx-zynqmp,10/14] UBUNTU: SAUCE: dts: zynqmp-sck-kd-g-revA: Enable uart0 for KD240

Message ID 20240822091117.1760423-11-portia.stephens@canonical.com
State New
Headers show
Series Backport ps uart RS485 driver | expand

Commit Message

Portia Stephens Aug. 22, 2024, 9:11 a.m. UTC 
From: Wen-chien Jesse Sung <jesse.sung@canonical.com>

BugLink: https://bugs.launchpad.net/bugs/2055237

This is backported from commit 1dfb4885eaa3 linux-xlnx. This
change comes from a large syncing commit so this commit pulls out only
the required changes to enabled uart0.

Signed-off-by: Portia Stephens <portia.stephens@canonical.com>
---
 .../boot/dts/xilinx/zynqmp-sck-kd-g-revA.dts  | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dts
index 94cb63cc6a186..6bfb2594bda8c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dts
@@ -171,6 +171,30 @@  conf-tx {
 		};
 	};
 
+	pinctrl_uart0_default: uart0-default {
+		conf {
+			groups = "uart0_17_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			drive-strength = <12>;
+		};
+
+		conf-rx {
+			pins = "MIO70";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO71";
+			bias-disable;
+		};
+
+		mux {
+			groups = "uart0_17_grp";
+			function = "uart0";
+		};
+	};
+
 	pinctrl_uart1_default: uart1-default {
 		conf {
 			groups = "uart1_9_grp";
@@ -321,6 +345,13 @@  mux {
 	};
 };
 
+&uart0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0_default>;
+	assigned-clock-rates = <100000000>;
+};
+
 &uart1 {
 	status = "okay";
 	pinctrl-names = "default";