| Message ID | 20231023132004.27743-1-stefan.bader@canonical.com |
|---|---|
| State | New |
| Headers | show |
| Series | [SRU,M/L/J] misc: rtsx: Fix some platforms can not boot and move the l1ss judgment to probe | expand |
On 10/23/23 7:20 AM, Stefan Bader wrote: > From: Ricky WU <ricky_wu@realtek.com> > > BugLink: https://bugs.launchpad.net/bugs/2040157 > > commit 101bd907b424 ("misc: rtsx: judge ASPM Mode to set PETXCFG Reg") > some readers no longer force #CLKREQ to low > when the system need to enter ASPM. > But some platform maybe not implement complete ASPM? > it causes some platforms can not boot > > Like in the past only the platform support L1ss we release the #CLKREQ. > Move the judgment (L1ss) to probe, > we think read config space one time when the driver start is enough > > Fixes: 101bd907b424 ("misc: rtsx: judge ASPM Mode to set PETXCFG Reg") > Cc: stable <stable@kernel.org> > Reported-by: Paul Grandperrin <paul.grandperrin@gmail.com> > Signed-off-by: Ricky Wu <ricky_wu@realtek.com> > Tested-By: Jade Lovelace <lists@jade.fyi> > Link: https://lore.kernel.org/r/37b1afb997f14946a8784c73d1f9a4f5@realtek.com > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > (cherry picked from commit 0e4cac557531a4c93de108d9ff11329fcad482ff) > Signed-off-by: Stefan Bader <stefan.bader@canonical.com> > --- > > For Mantic broken 6.5.0-rc6 and fixed 6.5.6 (we are at 6.5.3). > For Lunar pending as part of stable patchset 2023-10-10. > For Jammy pending as part of v5.15.127 upstream stable (fix in > v5.15.134) > > > drivers/misc/cardreader/rts5227.c | 55 ++++------------------------ > drivers/misc/cardreader/rts5228.c | 57 +++++++++--------------------- > drivers/misc/cardreader/rts5249.c | 56 ++++------------------------- > drivers/misc/cardreader/rts5260.c | 43 +++++++--------------- > drivers/misc/cardreader/rts5261.c | 52 +++++++-------------------- > drivers/misc/cardreader/rtsx_pcr.c | 51 +++++++++++++++++++++++--- > 6 files changed, 102 insertions(+), 212 deletions(-) > > diff --git a/drivers/misc/cardreader/rts5227.c b/drivers/misc/cardreader/rts5227.c > index 3dae5e3a1697..cd512284bfb3 100644 > --- a/drivers/misc/cardreader/rts5227.c > +++ b/drivers/misc/cardreader/rts5227.c > @@ -83,63 +83,20 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr) > > static void rts5227_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > if (CHK_PCI_PID(pcr, 0x522A)) { > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > + else > + rtsx_pci_enable_oobs_polling(pcr); > } > > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > - > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > - > - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > - | PM_L1_1_EN | PM_L1_2_EN)) > - option->force_clkreq_0 = false; > - else > - option->force_clkreq_0 = true; > - > } > > static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) > @@ -195,7 +152,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) > } > } > > - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) > + if (option->force_clkreq_0) > rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > diff --git a/drivers/misc/cardreader/rts5228.c b/drivers/misc/cardreader/rts5228.c > index f4ab09439da7..0c7f10bcf6f1 100644 > --- a/drivers/misc/cardreader/rts5228.c > +++ b/drivers/misc/cardreader/rts5228.c > @@ -386,59 +386,25 @@ static void rts5228_process_ocp(struct rtsx_pcr *pcr) > > static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > + rtsx_pci_enable_oobs_polling(pcr); > > rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > - if (option->ltr_en) { > - u16 val; > > - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_en) { > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > > rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, > CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); > @@ -469,6 +435,17 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) > else > rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); > > if (pcr->rtd3_en) { > diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c > index 47ab72a43256..6c81040e18be 100644 > --- a/drivers/misc/cardreader/rts5249.c > +++ b/drivers/misc/cardreader/rts5249.c > @@ -86,64 +86,22 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) > > static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > struct rtsx_cr_option *option = &(pcr->option); > - u32 lval; > - > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > > if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > + else > + rtsx_pci_enable_oobs_polling(pcr); > } > > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > -static int rts5249_init_from_hw(struct rtsx_pcr *pcr) > -{ > - struct rtsx_cr_option *option = &(pcr->option); > - > - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > - | PM_L1_1_EN | PM_L1_2_EN)) > - option->force_clkreq_0 = false; > - else > - option->force_clkreq_0 = true; > - > - return 0; > -} > - > static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) > { > /* Set relink_time to 0 */ > @@ -276,7 +234,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) > struct rtsx_cr_option *option = &(pcr->option); > > rts5249_init_from_cfg(pcr); > - rts5249_init_from_hw(pcr); > > rtsx_pci_init_cmd(pcr); > > @@ -327,11 +284,12 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) > } > } > > + > /* > * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > * to drive low, and we forcibly request clock. > */ > - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) > + if (option->force_clkreq_0) > rtsx_pci_write_register(pcr, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c > index 79b18f6f73a8..d2d3a6ccb8f7 100644 > --- a/drivers/misc/cardreader/rts5260.c > +++ b/drivers/misc/cardreader/rts5260.c > @@ -480,47 +480,19 @@ static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr) > > static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > struct rtsx_cr_option *option = &pcr->option; > - u32 lval; > - > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > > rts5260_pwr_saving_setting(pcr); > > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > > /* Set mcu_cnt to 7 to ensure data can be sampled properly */ > rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07); > @@ -539,6 +511,17 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) > > rts5260_init_hw(pcr); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); > > return 0; > diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c > index 94af6bf8a25a..67252512a132 100644 > --- a/drivers/misc/cardreader/rts5261.c > +++ b/drivers/misc/cardreader/rts5261.c > @@ -454,54 +454,17 @@ static void rts5261_init_from_hw(struct rtsx_pcr *pcr) > > static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > - > - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > u32 val; > > rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, > @@ -547,6 +510,17 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) > else > rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); > > if (pcr->rtd3_en) { > diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c > index a3f4b52bb159..a30751ad3733 100644 > --- a/drivers/misc/cardreader/rtsx_pcr.c > +++ b/drivers/misc/cardreader/rtsx_pcr.c > @@ -1326,11 +1326,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) > return err; > } > > - if (pcr->aspm_mode == ASPM_MODE_REG) { > + if (pcr->aspm_mode == ASPM_MODE_REG) > rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); > - rtsx_pci_write_register(pcr, PETXCFG, > - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > - } > > /* No CD interrupt if probing driver with card inserted. > * So we need to initialize pcr->card_exist here. > @@ -1345,7 +1342,9 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) > > static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) > { > - int err; > + struct rtsx_cr_option *option = &(pcr->option); > + int err, l1ss; > + u32 lval; > u16 cfg_val; > u8 val; > > @@ -1430,6 +1429,48 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) > pcr->aspm_enabled = true; > } > > + l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); > + if (l1ss) { > + pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); > + > + if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > + rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > + else > + rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > + > + if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > + rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > + else > + rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > + > + if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > + rtsx_set_dev_flag(pcr, PM_L1_1_EN); > + else > + rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > + > + if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > + rtsx_set_dev_flag(pcr, PM_L1_2_EN); > + else > + rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > + > + pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); > + if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) { > + option->ltr_enabled = true; > + option->ltr_active = true; > + } else { > + option->ltr_enabled = false; > + } > + > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > + option->force_clkreq_0 = false; > + else > + option->force_clkreq_0 = true; > + } else { > + option->ltr_enabled = false; > + option->force_clkreq_0 = true; > + } > + > if (pcr->ops->fetch_vendor_settings) > pcr->ops->fetch_vendor_settings(pcr); > Acked-by: Tim Gardner <tim.gardner@canonical.com> This patch certainly gets rid of a bunch of duplicate code.
On 23/10/2023 15:20, Stefan Bader wrote: > From: Ricky WU <ricky_wu@realtek.com> > > BugLink: https://bugs.launchpad.net/bugs/2040157 > > commit 101bd907b424 ("misc: rtsx: judge ASPM Mode to set PETXCFG Reg") > some readers no longer force #CLKREQ to low > when the system need to enter ASPM. > But some platform maybe not implement complete ASPM? > it causes some platforms can not boot > > Like in the past only the platform support L1ss we release the #CLKREQ. > Move the judgment (L1ss) to probe, > we think read config space one time when the driver start is enough > > Fixes: 101bd907b424 ("misc: rtsx: judge ASPM Mode to set PETXCFG Reg") > Cc: stable <stable@kernel.org> > Reported-by: Paul Grandperrin <paul.grandperrin@gmail.com> > Signed-off-by: Ricky Wu <ricky_wu@realtek.com> > Tested-By: Jade Lovelace <lists@jade.fyi> > Link: https://lore.kernel.org/r/37b1afb997f14946a8784c73d1f9a4f5@realtek.com > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > (cherry picked from commit 0e4cac557531a4c93de108d9ff11329fcad482ff) > Signed-off-by: Stefan Bader <stefan.bader@canonical.com> > --- > > For Mantic broken 6.5.0-rc6 and fixed 6.5.6 (we are at 6.5.3). > For Lunar pending as part of stable patchset 2023-10-10. > For Jammy pending as part of v5.15.127 upstream stable (fix in > v5.15.134) > > > drivers/misc/cardreader/rts5227.c | 55 ++++------------------------ > drivers/misc/cardreader/rts5228.c | 57 +++++++++--------------------- > drivers/misc/cardreader/rts5249.c | 56 ++++------------------------- > drivers/misc/cardreader/rts5260.c | 43 +++++++--------------- > drivers/misc/cardreader/rts5261.c | 52 +++++++-------------------- > drivers/misc/cardreader/rtsx_pcr.c | 51 +++++++++++++++++++++++--- > 6 files changed, 102 insertions(+), 212 deletions(-) > > diff --git a/drivers/misc/cardreader/rts5227.c b/drivers/misc/cardreader/rts5227.c > index 3dae5e3a1697..cd512284bfb3 100644 > --- a/drivers/misc/cardreader/rts5227.c > +++ b/drivers/misc/cardreader/rts5227.c > @@ -83,63 +83,20 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr) > > static void rts5227_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > if (CHK_PCI_PID(pcr, 0x522A)) { > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > + else > + rtsx_pci_enable_oobs_polling(pcr); > } > > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > - > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > - > - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > - | PM_L1_1_EN | PM_L1_2_EN)) > - option->force_clkreq_0 = false; > - else > - option->force_clkreq_0 = true; > - > } > > static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) > @@ -195,7 +152,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) > } > } > > - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) > + if (option->force_clkreq_0) > rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > diff --git a/drivers/misc/cardreader/rts5228.c b/drivers/misc/cardreader/rts5228.c > index f4ab09439da7..0c7f10bcf6f1 100644 > --- a/drivers/misc/cardreader/rts5228.c > +++ b/drivers/misc/cardreader/rts5228.c > @@ -386,59 +386,25 @@ static void rts5228_process_ocp(struct rtsx_pcr *pcr) > > static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > + rtsx_pci_enable_oobs_polling(pcr); > > rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > - if (option->ltr_en) { > - u16 val; > > - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_en) { > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > > rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, > CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); > @@ -469,6 +435,17 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) > else > rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); > > if (pcr->rtd3_en) { > diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c > index 47ab72a43256..6c81040e18be 100644 > --- a/drivers/misc/cardreader/rts5249.c > +++ b/drivers/misc/cardreader/rts5249.c > @@ -86,64 +86,22 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) > > static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > struct rtsx_cr_option *option = &(pcr->option); > - u32 lval; > - > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > > if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > + else > + rtsx_pci_enable_oobs_polling(pcr); > } > > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > -static int rts5249_init_from_hw(struct rtsx_pcr *pcr) > -{ > - struct rtsx_cr_option *option = &(pcr->option); > - > - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > - | PM_L1_1_EN | PM_L1_2_EN)) > - option->force_clkreq_0 = false; > - else > - option->force_clkreq_0 = true; > - > - return 0; > -} > - > static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) > { > /* Set relink_time to 0 */ > @@ -276,7 +234,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) > struct rtsx_cr_option *option = &(pcr->option); > > rts5249_init_from_cfg(pcr); > - rts5249_init_from_hw(pcr); > > rtsx_pci_init_cmd(pcr); > > @@ -327,11 +284,12 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) > } > } > > + > /* > * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > * to drive low, and we forcibly request clock. > */ > - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) > + if (option->force_clkreq_0) > rtsx_pci_write_register(pcr, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c > index 79b18f6f73a8..d2d3a6ccb8f7 100644 > --- a/drivers/misc/cardreader/rts5260.c > +++ b/drivers/misc/cardreader/rts5260.c > @@ -480,47 +480,19 @@ static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr) > > static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > struct rtsx_cr_option *option = &pcr->option; > - u32 lval; > - > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > > rts5260_pwr_saving_setting(pcr); > > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > > /* Set mcu_cnt to 7 to ensure data can be sampled properly */ > rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07); > @@ -539,6 +511,17 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) > > rts5260_init_hw(pcr); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); > > return 0; > diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c > index 94af6bf8a25a..67252512a132 100644 > --- a/drivers/misc/cardreader/rts5261.c > +++ b/drivers/misc/cardreader/rts5261.c > @@ -454,54 +454,17 @@ static void rts5261_init_from_hw(struct rtsx_pcr *pcr) > > static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > - > - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > u32 val; > > rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, > @@ -547,6 +510,17 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) > else > rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); > > if (pcr->rtd3_en) { > diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c > index a3f4b52bb159..a30751ad3733 100644 > --- a/drivers/misc/cardreader/rtsx_pcr.c > +++ b/drivers/misc/cardreader/rtsx_pcr.c > @@ -1326,11 +1326,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) > return err; > } > > - if (pcr->aspm_mode == ASPM_MODE_REG) { > + if (pcr->aspm_mode == ASPM_MODE_REG) > rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); > - rtsx_pci_write_register(pcr, PETXCFG, > - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > - } > > /* No CD interrupt if probing driver with card inserted. > * So we need to initialize pcr->card_exist here. > @@ -1345,7 +1342,9 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) > > static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) > { > - int err; > + struct rtsx_cr_option *option = &(pcr->option); > + int err, l1ss; > + u32 lval; > u16 cfg_val; > u8 val; > > @@ -1430,6 +1429,48 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) > pcr->aspm_enabled = true; > } > > + l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); > + if (l1ss) { > + pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); > + > + if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > + rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > + else > + rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > + > + if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > + rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > + else > + rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > + > + if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > + rtsx_set_dev_flag(pcr, PM_L1_1_EN); > + else > + rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > + > + if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > + rtsx_set_dev_flag(pcr, PM_L1_2_EN); > + else > + rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > + > + pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); > + if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) { > + option->ltr_enabled = true; > + option->ltr_active = true; > + } else { > + option->ltr_enabled = false; > + } > + > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > + option->force_clkreq_0 = false; > + else > + option->force_clkreq_0 = true; > + } else { > + option->ltr_enabled = false; > + option->force_clkreq_0 = true; > + } > + > if (pcr->ops->fetch_vendor_settings) > pcr->ops->fetch_vendor_settings(pcr); > Acked-by: Roxana Nicolescu <roxana.nicolescu@canonical.com>
On 23.10.23 15:20, Stefan Bader wrote: > From: Ricky WU <ricky_wu@realtek.com> > > BugLink: https://bugs.launchpad.net/bugs/2040157 > > commit 101bd907b424 ("misc: rtsx: judge ASPM Mode to set PETXCFG Reg") > some readers no longer force #CLKREQ to low > when the system need to enter ASPM. > But some platform maybe not implement complete ASPM? > it causes some platforms can not boot > > Like in the past only the platform support L1ss we release the #CLKREQ. > Move the judgment (L1ss) to probe, > we think read config space one time when the driver start is enough > > Fixes: 101bd907b424 ("misc: rtsx: judge ASPM Mode to set PETXCFG Reg") > Cc: stable <stable@kernel.org> > Reported-by: Paul Grandperrin <paul.grandperrin@gmail.com> > Signed-off-by: Ricky Wu <ricky_wu@realtek.com> > Tested-By: Jade Lovelace <lists@jade.fyi> > Link: https://lore.kernel.org/r/37b1afb997f14946a8784c73d1f9a4f5@realtek.com > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > (cherry picked from commit 0e4cac557531a4c93de108d9ff11329fcad482ff) > Signed-off-by: Stefan Bader <stefan.bader@canonical.com> > --- > > For Mantic broken 6.5.0-rc6 and fixed 6.5.6 (we are at 6.5.3). > For Lunar pending as part of stable patchset 2023-10-10. > For Jammy pending as part of v5.15.127 upstream stable (fix in > v5.15.134) > > Applied to mantic,lunar,jammy:linux/master-next. Thanks. -Stefan > drivers/misc/cardreader/rts5227.c | 55 ++++------------------------ > drivers/misc/cardreader/rts5228.c | 57 +++++++++--------------------- > drivers/misc/cardreader/rts5249.c | 56 ++++------------------------- > drivers/misc/cardreader/rts5260.c | 43 +++++++--------------- > drivers/misc/cardreader/rts5261.c | 52 +++++++-------------------- > drivers/misc/cardreader/rtsx_pcr.c | 51 +++++++++++++++++++++++--- > 6 files changed, 102 insertions(+), 212 deletions(-) > > diff --git a/drivers/misc/cardreader/rts5227.c b/drivers/misc/cardreader/rts5227.c > index 3dae5e3a1697..cd512284bfb3 100644 > --- a/drivers/misc/cardreader/rts5227.c > +++ b/drivers/misc/cardreader/rts5227.c > @@ -83,63 +83,20 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr) > > static void rts5227_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > if (CHK_PCI_PID(pcr, 0x522A)) { > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > + else > + rtsx_pci_enable_oobs_polling(pcr); > } > > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > - > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > - > - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > - | PM_L1_1_EN | PM_L1_2_EN)) > - option->force_clkreq_0 = false; > - else > - option->force_clkreq_0 = true; > - > } > > static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) > @@ -195,7 +152,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) > } > } > > - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) > + if (option->force_clkreq_0) > rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > diff --git a/drivers/misc/cardreader/rts5228.c b/drivers/misc/cardreader/rts5228.c > index f4ab09439da7..0c7f10bcf6f1 100644 > --- a/drivers/misc/cardreader/rts5228.c > +++ b/drivers/misc/cardreader/rts5228.c > @@ -386,59 +386,25 @@ static void rts5228_process_ocp(struct rtsx_pcr *pcr) > > static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > + rtsx_pci_enable_oobs_polling(pcr); > > rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > - if (option->ltr_en) { > - u16 val; > > - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_en) { > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > > rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, > CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); > @@ -469,6 +435,17 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) > else > rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); > > if (pcr->rtd3_en) { > diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c > index 47ab72a43256..6c81040e18be 100644 > --- a/drivers/misc/cardreader/rts5249.c > +++ b/drivers/misc/cardreader/rts5249.c > @@ -86,64 +86,22 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) > > static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > struct rtsx_cr_option *option = &(pcr->option); > - u32 lval; > - > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > > if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { > - if (0 == (lval & 0x0F)) > - rtsx_pci_enable_oobs_polling(pcr); > - else > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > rtsx_pci_disable_oobs_polling(pcr); > + else > + rtsx_pci_enable_oobs_polling(pcr); > } > > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > -static int rts5249_init_from_hw(struct rtsx_pcr *pcr) > -{ > - struct rtsx_cr_option *option = &(pcr->option); > - > - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > - | PM_L1_1_EN | PM_L1_2_EN)) > - option->force_clkreq_0 = false; > - else > - option->force_clkreq_0 = true; > - > - return 0; > -} > - > static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) > { > /* Set relink_time to 0 */ > @@ -276,7 +234,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) > struct rtsx_cr_option *option = &(pcr->option); > > rts5249_init_from_cfg(pcr); > - rts5249_init_from_hw(pcr); > > rtsx_pci_init_cmd(pcr); > > @@ -327,11 +284,12 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) > } > } > > + > /* > * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > * to drive low, and we forcibly request clock. > */ > - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) > + if (option->force_clkreq_0) > rtsx_pci_write_register(pcr, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c > index 79b18f6f73a8..d2d3a6ccb8f7 100644 > --- a/drivers/misc/cardreader/rts5260.c > +++ b/drivers/misc/cardreader/rts5260.c > @@ -480,47 +480,19 @@ static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr) > > static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > struct rtsx_cr_option *option = &pcr->option; > - u32 lval; > - > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > > rts5260_pwr_saving_setting(pcr); > > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > > /* Set mcu_cnt to 7 to ensure data can be sampled properly */ > rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07); > @@ -539,6 +511,17 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) > > rts5260_init_hw(pcr); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); > > return 0; > diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c > index 94af6bf8a25a..67252512a132 100644 > --- a/drivers/misc/cardreader/rts5261.c > +++ b/drivers/misc/cardreader/rts5261.c > @@ -454,54 +454,17 @@ static void rts5261_init_from_hw(struct rtsx_pcr *pcr) > > static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) > { > - struct pci_dev *pdev = pcr->pci; > - int l1ss; > - u32 lval; > struct rtsx_cr_option *option = &pcr->option; > > - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); > - if (!l1ss) > - return; > - > - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > - rtsx_set_dev_flag(pcr, PM_L1_1_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > - > - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > - rtsx_set_dev_flag(pcr, PM_L1_2_EN); > - else > - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > - > - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > if (option->ltr_en) { > - u16 val; > - > - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); > - if (val & PCI_EXP_DEVCTL2_LTR_EN) { > - option->ltr_enabled = true; > - option->ltr_active = true; > + if (option->ltr_enabled) > rtsx_set_ltr_latency(pcr, option->ltr_active_latency); > - } else { > - option->ltr_enabled = false; > - } > } > } > > static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) > { > + struct rtsx_cr_option *option = &pcr->option; > u32 val; > > rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, > @@ -547,6 +510,17 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) > else > rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); > > + /* > + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced > + * to drive low, and we forcibly request clock. > + */ > + if (option->force_clkreq_0) > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > + else > + rtsx_pci_write_register(pcr, PETXCFG, > + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > + > rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); > > if (pcr->rtd3_en) { > diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c > index a3f4b52bb159..a30751ad3733 100644 > --- a/drivers/misc/cardreader/rtsx_pcr.c > +++ b/drivers/misc/cardreader/rtsx_pcr.c > @@ -1326,11 +1326,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) > return err; > } > > - if (pcr->aspm_mode == ASPM_MODE_REG) { > + if (pcr->aspm_mode == ASPM_MODE_REG) > rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); > - rtsx_pci_write_register(pcr, PETXCFG, > - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > - } > > /* No CD interrupt if probing driver with card inserted. > * So we need to initialize pcr->card_exist here. > @@ -1345,7 +1342,9 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) > > static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) > { > - int err; > + struct rtsx_cr_option *option = &(pcr->option); > + int err, l1ss; > + u32 lval; > u16 cfg_val; > u8 val; > > @@ -1430,6 +1429,48 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) > pcr->aspm_enabled = true; > } > > + l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); > + if (l1ss) { > + pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); > + > + if (lval & PCI_L1SS_CTL1_ASPM_L1_1) > + rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); > + else > + rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); > + > + if (lval & PCI_L1SS_CTL1_ASPM_L1_2) > + rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); > + else > + rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); > + > + if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) > + rtsx_set_dev_flag(pcr, PM_L1_1_EN); > + else > + rtsx_clear_dev_flag(pcr, PM_L1_1_EN); > + > + if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) > + rtsx_set_dev_flag(pcr, PM_L1_2_EN); > + else > + rtsx_clear_dev_flag(pcr, PM_L1_2_EN); > + > + pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); > + if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) { > + option->ltr_enabled = true; > + option->ltr_active = true; > + } else { > + option->ltr_enabled = false; > + } > + > + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN > + | PM_L1_1_EN | PM_L1_2_EN)) > + option->force_clkreq_0 = false; > + else > + option->force_clkreq_0 = true; > + } else { > + option->ltr_enabled = false; > + option->force_clkreq_0 = true; > + } > + > if (pcr->ops->fetch_vendor_settings) > pcr->ops->fetch_vendor_settings(pcr); >
diff --git a/drivers/misc/cardreader/rts5227.c b/drivers/misc/cardreader/rts5227.c index 3dae5e3a1697..cd512284bfb3 100644 --- a/drivers/misc/cardreader/rts5227.c +++ b/drivers/misc/cardreader/rts5227.c @@ -83,63 +83,20 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr) static void rts5227_init_from_cfg(struct rtsx_pcr *pcr) { - struct pci_dev *pdev = pcr->pci; - int l1ss; - u32 lval; struct rtsx_cr_option *option = &pcr->option; - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!l1ss) - return; - - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); - if (CHK_PCI_PID(pcr, 0x522A)) { - if (0 == (lval & 0x0F)) - rtsx_pci_enable_oobs_polling(pcr); - else + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN + | PM_L1_1_EN | PM_L1_2_EN)) rtsx_pci_disable_oobs_polling(pcr); + else + rtsx_pci_enable_oobs_polling(pcr); } - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); - else - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); - else - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) - rtsx_set_dev_flag(pcr, PM_L1_1_EN); - else - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) - rtsx_set_dev_flag(pcr, PM_L1_2_EN); - else - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); - if (option->ltr_en) { - u16 val; - - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { - option->ltr_enabled = true; - option->ltr_active = true; + if (option->ltr_enabled) rtsx_set_ltr_latency(pcr, option->ltr_active_latency); - } else { - option->ltr_enabled = false; - } } - - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN - | PM_L1_1_EN | PM_L1_2_EN)) - option->force_clkreq_0 = false; - else - option->force_clkreq_0 = true; - } static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) @@ -195,7 +152,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) } } - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) + if (option->force_clkreq_0) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); else diff --git a/drivers/misc/cardreader/rts5228.c b/drivers/misc/cardreader/rts5228.c index f4ab09439da7..0c7f10bcf6f1 100644 --- a/drivers/misc/cardreader/rts5228.c +++ b/drivers/misc/cardreader/rts5228.c @@ -386,59 +386,25 @@ static void rts5228_process_ocp(struct rtsx_pcr *pcr) static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) { - struct pci_dev *pdev = pcr->pci; - int l1ss; - u32 lval; struct rtsx_cr_option *option = &pcr->option; - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!l1ss) - return; - - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); - - if (0 == (lval & 0x0F)) - rtsx_pci_enable_oobs_polling(pcr); - else + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN + | PM_L1_1_EN | PM_L1_2_EN)) rtsx_pci_disable_oobs_polling(pcr); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); - else - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); - else - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) - rtsx_set_dev_flag(pcr, PM_L1_1_EN); else - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) - rtsx_set_dev_flag(pcr, PM_L1_2_EN); - else - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); + rtsx_pci_enable_oobs_polling(pcr); rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); - if (option->ltr_en) { - u16 val; - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { - option->ltr_enabled = true; - option->ltr_active = true; + if (option->ltr_en) { + if (option->ltr_enabled) rtsx_set_ltr_latency(pcr, option->ltr_active_latency); - } else { - option->ltr_enabled = false; - } } } static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) { + struct rtsx_cr_option *option = &pcr->option; rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); @@ -469,6 +435,17 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) else rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); + /* + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced + * to drive low, and we forcibly request clock. + */ + if (option->force_clkreq_0) + rtsx_pci_write_register(pcr, PETXCFG, + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); + else + rtsx_pci_write_register(pcr, PETXCFG, + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); + rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); if (pcr->rtd3_en) { diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c index 47ab72a43256..6c81040e18be 100644 --- a/drivers/misc/cardreader/rts5249.c +++ b/drivers/misc/cardreader/rts5249.c @@ -86,64 +86,22 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) { - struct pci_dev *pdev = pcr->pci; - int l1ss; struct rtsx_cr_option *option = &(pcr->option); - u32 lval; - - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!l1ss) - return; - - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { - if (0 == (lval & 0x0F)) - rtsx_pci_enable_oobs_polling(pcr); - else + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN + | PM_L1_1_EN | PM_L1_2_EN)) rtsx_pci_disable_oobs_polling(pcr); + else + rtsx_pci_enable_oobs_polling(pcr); } - - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) - rtsx_set_dev_flag(pcr, PM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) - rtsx_set_dev_flag(pcr, PM_L1_2_EN); - if (option->ltr_en) { - u16 val; - - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { - option->ltr_enabled = true; - option->ltr_active = true; + if (option->ltr_enabled) rtsx_set_ltr_latency(pcr, option->ltr_active_latency); - } else { - option->ltr_enabled = false; - } } } -static int rts5249_init_from_hw(struct rtsx_pcr *pcr) -{ - struct rtsx_cr_option *option = &(pcr->option); - - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN - | PM_L1_1_EN | PM_L1_2_EN)) - option->force_clkreq_0 = false; - else - option->force_clkreq_0 = true; - - return 0; -} - static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) { /* Set relink_time to 0 */ @@ -276,7 +234,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) struct rtsx_cr_option *option = &(pcr->option); rts5249_init_from_cfg(pcr); - rts5249_init_from_hw(pcr); rtsx_pci_init_cmd(pcr); @@ -327,11 +284,12 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) } } + /* * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced * to drive low, and we forcibly request clock. */ - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) + if (option->force_clkreq_0) rtsx_pci_write_register(pcr, PETXCFG, FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); else diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c index 79b18f6f73a8..d2d3a6ccb8f7 100644 --- a/drivers/misc/cardreader/rts5260.c +++ b/drivers/misc/cardreader/rts5260.c @@ -480,47 +480,19 @@ static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr) static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) { - struct pci_dev *pdev = pcr->pci; - int l1ss; struct rtsx_cr_option *option = &pcr->option; - u32 lval; - - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!l1ss) - return; - - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) - rtsx_set_dev_flag(pcr, PM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) - rtsx_set_dev_flag(pcr, PM_L1_2_EN); rts5260_pwr_saving_setting(pcr); if (option->ltr_en) { - u16 val; - - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { - option->ltr_enabled = true; - option->ltr_active = true; + if (option->ltr_enabled) rtsx_set_ltr_latency(pcr, option->ltr_active_latency); - } else { - option->ltr_enabled = false; - } } } static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) { + struct rtsx_cr_option *option = &pcr->option; /* Set mcu_cnt to 7 to ensure data can be sampled properly */ rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07); @@ -539,6 +511,17 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) rts5260_init_hw(pcr); + /* + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced + * to drive low, and we forcibly request clock. + */ + if (option->force_clkreq_0) + rtsx_pci_write_register(pcr, PETXCFG, + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); + else + rtsx_pci_write_register(pcr, PETXCFG, + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); + rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); return 0; diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c index 94af6bf8a25a..67252512a132 100644 --- a/drivers/misc/cardreader/rts5261.c +++ b/drivers/misc/cardreader/rts5261.c @@ -454,54 +454,17 @@ static void rts5261_init_from_hw(struct rtsx_pcr *pcr) static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) { - struct pci_dev *pdev = pcr->pci; - int l1ss; - u32 lval; struct rtsx_cr_option *option = &pcr->option; - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!l1ss) - return; - - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); - else - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); - else - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) - rtsx_set_dev_flag(pcr, PM_L1_1_EN); - else - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); - - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) - rtsx_set_dev_flag(pcr, PM_L1_2_EN); - else - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); - - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); if (option->ltr_en) { - u16 val; - - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { - option->ltr_enabled = true; - option->ltr_active = true; + if (option->ltr_enabled) rtsx_set_ltr_latency(pcr, option->ltr_active_latency); - } else { - option->ltr_enabled = false; - } } } static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) { + struct rtsx_cr_option *option = &pcr->option; u32 val; rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, @@ -547,6 +510,17 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) else rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); + /* + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced + * to drive low, and we forcibly request clock. + */ + if (option->force_clkreq_0) + rtsx_pci_write_register(pcr, PETXCFG, + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); + else + rtsx_pci_write_register(pcr, PETXCFG, + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); + rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); if (pcr->rtd3_en) { diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c index a3f4b52bb159..a30751ad3733 100644 --- a/drivers/misc/cardreader/rtsx_pcr.c +++ b/drivers/misc/cardreader/rtsx_pcr.c @@ -1326,11 +1326,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) return err; } - if (pcr->aspm_mode == ASPM_MODE_REG) { + if (pcr->aspm_mode == ASPM_MODE_REG) rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); - rtsx_pci_write_register(pcr, PETXCFG, - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); - } /* No CD interrupt if probing driver with card inserted. * So we need to initialize pcr->card_exist here. @@ -1345,7 +1342,9 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) { - int err; + struct rtsx_cr_option *option = &(pcr->option); + int err, l1ss; + u32 lval; u16 cfg_val; u8 val; @@ -1430,6 +1429,48 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) pcr->aspm_enabled = true; } + l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); + if (l1ss) { + pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); + + if (lval & PCI_L1SS_CTL1_ASPM_L1_1) + rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); + else + rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); + + if (lval & PCI_L1SS_CTL1_ASPM_L1_2) + rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); + else + rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); + + if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) + rtsx_set_dev_flag(pcr, PM_L1_1_EN); + else + rtsx_clear_dev_flag(pcr, PM_L1_1_EN); + + if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) + rtsx_set_dev_flag(pcr, PM_L1_2_EN); + else + rtsx_clear_dev_flag(pcr, PM_L1_2_EN); + + pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); + if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) { + option->ltr_enabled = true; + option->ltr_active = true; + } else { + option->ltr_enabled = false; + } + + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN + | PM_L1_1_EN | PM_L1_2_EN)) + option->force_clkreq_0 = false; + else + option->force_clkreq_0 = true; + } else { + option->ltr_enabled = false; + option->force_clkreq_0 = true; + } + if (pcr->ops->fetch_vendor_settings) pcr->ops->fetch_vendor_settings(pcr);