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Fri, 25 Feb 2022 12:55:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJxOUIpaf5VeLjkw0qIlBF2rVkwGcsXOEEK03PwK/RBqcvYr3VvUcRhWyXQU2U16MQ/+4hqleg== X-Received: by 2002:adf:e185:0:b0:1e2:6421:f2d0 with SMTP id az5-20020adfe185000000b001e26421f2d0mr7564806wrb.703.1645822510627; Fri, 25 Feb 2022 12:55:10 -0800 (PST) Received: from localhost ([2a01:4b00:85fd:d700:5ec7:56fa:4ff4:7c95]) by smtp.gmail.com with ESMTPSA id p30-20020a1c545e000000b003811f9102c0sm5318181wmi.32.2022.02.25.12.55.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 12:55:10 -0800 (PST) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [linux-riscv][J][PATCHv2 13/17] riscv: dts: sifive: Group tuples in interrupt properties Date: Fri, 25 Feb 2022 20:54:46 +0000 Message-Id: <20220225205450.23844-14-dimitri.ledkov@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220225205450.23844-1-dimitri.ledkov@canonical.com> References: <20220225205450.23844-1-dimitri.ledkov@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Geert Uytterhoeven To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Palmer Dabbelt (cherry picked from commit cc79be0e0c9f9e529641b286af54dc5ed26d9407) BugLink: https://bugs.launchpad.net/bugs/1962010 Signed-off-by: Dimitri John Ledkov --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++---------- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0655b5c420..0caca0ccf6 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <53>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci"; @@ -170,7 +170,8 @@ dma: dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; }; uart1: serial@10011000 { @@ -243,7 +244,7 @@ pwm0: pwm@10020000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; + interrupts = <42>, <43>, <44>, <45>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; @@ -252,7 +253,7 @@ pwm1: pwm@10021000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; + interrupts = <46>, <47>, <48>, <49>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; @@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 3095d82343..e011621098 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu740-c000-prci"; @@ -273,7 +273,7 @@ ccache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 21 22 20>; + interrupts = <19>, <21>, <22>, <20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 {