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Fri, 25 Feb 2022 12:33:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJwQuon80MHA9OJbrafbVIrNz2SLPqgyGf58vBbbksXwoCpRZB/JnsLvOGnnH0vUklpbuL3tyA== X-Received: by 2002:a05:600c:3785:b0:380:ce6c:cece with SMTP id o5-20020a05600c378500b00380ce6ccecemr4193171wmr.0.1645821205140; Fri, 25 Feb 2022 12:33:25 -0800 (PST) Received: from localhost ([2a01:4b00:85fd:d700:5ec7:56fa:4ff4:7c95]) by smtp.gmail.com with ESMTPSA id u14-20020adfed4e000000b001e3323611e5sm3268042wro.26.2022.02.25.12.33.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 12:33:24 -0800 (PST) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [linux-riscv][J][PATCH 14/17] riscv: dts: sifive: Group tuples in register properties Date: Fri, 25 Feb 2022 20:32:58 +0000 Message-Id: <20220225203301.20851-15-dimitri.ledkov@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220225203301.20851-1-dimitri.ledkov@canonical.com> References: <20220225203301.20851-1-dimitri.ledkov@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Geert Uytterhoeven To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Palmer Dabbelt (cherry picked from commit 8e9b1c9555c1128bcda473383ae9ba3742b59fa8) BugLink: https://bugs.launchpad.net/bugs/1960420 Signed-off-by: Dimitri John Ledkov --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0caca0ccf6..e2efcf0821 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -196,8 +196,8 @@ i2c0: i2c@10030000 { }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -207,8 +207,8 @@ qspi0: spi@10040000 { }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -230,8 +230,8 @@ eth0: ethernet@10090000 { compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci PRCI_CLK_GEMGXLPLL>,