diff mbox series

[1/1,SRU,J] UBUNTU: SAUCE: iommu: intel-ipu: use IOMMU passthrough mode for Intel IPUs

Message ID 20220223022125.1244670-2-vicamo.yang@canonical.com
State New
Headers show
Series use IOMMU passthrough mode for Intel IPUs | expand

Commit Message

You-Sheng Yang Feb. 23, 2022, 2:21 a.m. UTC 
From: zouxiaoh <xiaohong.zou@intel.com>

BugLink: https://bugs.launchpad.net/bugs/1958004

Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
The IPU driver allocates its own page table that is not mapped
via the DMA, and thus the Intel IOMMU driver blocks access giving
this error: DMAR: DRHD: handling fault status reg 3 DMAR:
[DMA Read] Request device [00:05.0] PASID ffffffff
fault addr 76406000 [fault reason 06] PTE Read access is not set
As IPU is not an external facing device which is not risky, so use
IOMMU passthrough mode for Intel IPUs.

Change-Id: I6dcccdadac308cf42e20a18e1b593381391e3e6b
Depends-On: Iacd67578e8c6a9b9ac73285f52b4081b72fb68a6
Tracked-On: #JIITL8-411
Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
Signed-off-by: zouxiaoh <xiaohong.zou@intel.com>
Signed-off-by: Xu Chongyang <chongyang.xu@intel.com>
(cherry picked from https://github.com/intel/ipu6-drivers/blob/5d5526d2b2811aa52590c2fa513ba989e7e594ab/patch/IOMMU-passthrough-for-intel-ipu.diff)
Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
 drivers/iommu/intel/iommu.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Kai-Heng Feng Feb. 23, 2022, 2:29 a.m. UTC | #1 
On Wed, Feb 23, 2022 at 10:22 AM You-Sheng Yang
<vicamo.yang@canonical.com> wrote:
>
> From: zouxiaoh <xiaohong.zou@intel.com>
>
> BugLink: https://bugs.launchpad.net/bugs/1958004
>
> Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
> The IPU driver allocates its own page table that is not mapped
> via the DMA, and thus the Intel IOMMU driver blocks access giving
> this error: DMAR: DRHD: handling fault status reg 3 DMAR:
> [DMA Read] Request device [00:05.0] PASID ffffffff
> fault addr 76406000 [fault reason 06] PTE Read access is not set
> As IPU is not an external facing device which is not risky, so use
> IOMMU passthrough mode for Intel IPUs.

Many non-external facing devices also use DMA mode, so this is not a
good justification.

Can we ask whether PT mode is used for IPU6 under ChromeOS and Windows?

Kai-Heng

>
> Change-Id: I6dcccdadac308cf42e20a18e1b593381391e3e6b
> Depends-On: Iacd67578e8c6a9b9ac73285f52b4081b72fb68a6
> Tracked-On: #JIITL8-411
> Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
> Signed-off-by: zouxiaoh <xiaohong.zou@intel.com>
> Signed-off-by: Xu Chongyang <chongyang.xu@intel.com>
> (cherry picked from https://github.com/intel/ipu6-drivers/blob/5d5526d2b2811aa52590c2fa513ba989e7e594ab/patch/IOMMU-passthrough-for-intel-ipu.diff)
> Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
> ---
>  drivers/iommu/intel/iommu.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 78f8c8e6803e..ff451b4e4a5a 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -57,6 +57,12 @@
>  #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
>  #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
>  #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
> +#define IS_INTEL_IPU(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL &&   \
> +                          ((pdev)->device == 0x9a19 ||         \
> +                           (pdev)->device == 0x9a39 ||         \
> +                           (pdev)->device == 0x4e19 ||         \
> +                           (pdev)->device == 0x465d ||         \
> +                           (pdev)->device == 0x1919))
>  #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
>
>  #define IOAPIC_RANGE_START     (0xfee00000)
> @@ -335,12 +341,14 @@ int intel_iommu_enabled = 0;
>  EXPORT_SYMBOL_GPL(intel_iommu_enabled);
>
>  static int dmar_map_gfx = 1;
> +static int dmar_map_ipu = 1;
>  static int intel_iommu_superpage = 1;
>  static int iommu_identity_mapping;
>  static int iommu_skip_te_disable;
>
>  #define IDENTMAP_GFX           2
>  #define IDENTMAP_AZALIA                4
> +#define IDENTMAP_IPU           8
>
>  int intel_iommu_gfx_mapped;
>  EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
> @@ -2879,6 +2887,9 @@ static int device_def_domain_type(struct device *dev)
>
>                 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
>                         return IOMMU_DOMAIN_IDENTITY;
> +
> +               if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev))
> +                       return IOMMU_DOMAIN_IDENTITY;
>         }
>
>         return 0;
> @@ -3315,6 +3326,9 @@ static int __init init_dmars(void)
>         if (!dmar_map_gfx)
>                 iommu_identity_mapping |= IDENTMAP_GFX;
>
> +       if (!dmar_map_ipu)
> +               iommu_identity_mapping |= IDENTMAP_IPU;
> +
>         check_tylersburg_isoch();
>
>         ret = si_domain_init(hw_pass_through);
> @@ -5607,6 +5621,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev)
>         dmar_map_gfx = 0;
>  }
>
> +static void quirk_iommu_ipu(struct pci_dev *dev)
> +{
> +       if (!IS_INTEL_IPU(dev))
> +               return;
> +
> +       if (risky_device(dev))
> +               return;
> +
> +       pci_info(dev, "Passthrough IOMMU for integrated Intel IPU\n");
> +       dmar_map_ipu = 0;
> +}
> +
>  /* G4x/GM45 integrated gfx dmar support is totally busted. */
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx);
> @@ -5642,6 +5668,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
>
> +/* disable IPU dmar support */
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu);
> +
>  static void quirk_iommu_rwbf(struct pci_dev *dev)
>  {
>         if (risky_device(dev))
> --
> 2.34.1
>
>
> --
> kernel-team mailing list
> kernel-team@lists.ubuntu.com
> https://lists.ubuntu.com/mailman/listinfo/kernel-team
You-Sheng Yang March 9, 2022, 7:08 a.m. UTC | #2 
On 2/23/22 10:29, Kai-Heng Feng wrote:
> Many non-external facing devices also use DMA mode, so this is not a
> good justification.
> 
> Can we ask whether PT mode is used for IPU6 under ChromeOS and Windows?
> 
> Kai-Heng

Has confirmed with Intel that ChromeOS is also using passthrough mode.
Paolo Pisati March 9, 2022, 2:14 p.m. UTC | #3 
On Wed, Mar 09, 2022 at 03:08:17PM +0800, You-Sheng Yang wrote:
> On 2/23/22 10:29, Kai-Heng Feng wrote:
> > Many non-external facing devices also use DMA mode, so this is not a
> > good justification.
> > 
> > Can we ask whether PT mode is used for IPU6 under ChromeOS and Windows?
> > 
> > Kai-Heng
> 
> Has confirmed with Intel that ChromeOS is also using passthrough mode.

Are you both happy with the outcome? Shall i apply the patch?
Kai-Heng Feng March 10, 2022, 2:26 a.m. UTC | #4 
On Wed, Mar 9, 2022 at 10:14 PM Paolo Pisati <paolo.pisati@canonical.com> wrote:
>
> On Wed, Mar 09, 2022 at 03:08:17PM +0800, You-Sheng Yang wrote:
> > On 2/23/22 10:29, Kai-Heng Feng wrote:
> > > Many non-external facing devices also use DMA mode, so this is not a
> > > good justification.
> > >
> > > Can we ask whether PT mode is used for IPU6 under ChromeOS and Windows?
> > >
> > > Kai-Heng
> >
> > Has confirmed with Intel that ChromeOS is also using passthrough mode.
>
> Are you both happy with the outcome? Shall i apply the patch?

I assume Google already reviewed the approach so the security impact
should be minimal.

So please apply the patch, thanks!

Kai-Heng

> --
> bye,
> p.
diff mbox series

Patch

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 78f8c8e6803e..ff451b4e4a5a 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -57,6 +57,12 @@ 
 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
 #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
+#define IS_INTEL_IPU(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL &&	\
+			   ((pdev)->device == 0x9a19 ||		\
+			    (pdev)->device == 0x9a39 ||		\
+			    (pdev)->device == 0x4e19 ||		\
+			    (pdev)->device == 0x465d ||		\
+			    (pdev)->device == 0x1919))
 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
 
 #define IOAPIC_RANGE_START	(0xfee00000)
@@ -335,12 +341,14 @@  int intel_iommu_enabled = 0;
 EXPORT_SYMBOL_GPL(intel_iommu_enabled);
 
 static int dmar_map_gfx = 1;
+static int dmar_map_ipu = 1;
 static int intel_iommu_superpage = 1;
 static int iommu_identity_mapping;
 static int iommu_skip_te_disable;
 
 #define IDENTMAP_GFX		2
 #define IDENTMAP_AZALIA		4
+#define IDENTMAP_IPU		8
 
 int intel_iommu_gfx_mapped;
 EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
@@ -2879,6 +2887,9 @@  static int device_def_domain_type(struct device *dev)
 
 		if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
 			return IOMMU_DOMAIN_IDENTITY;
+
+		if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev))
+			return IOMMU_DOMAIN_IDENTITY;
 	}
 
 	return 0;
@@ -3315,6 +3326,9 @@  static int __init init_dmars(void)
 	if (!dmar_map_gfx)
 		iommu_identity_mapping |= IDENTMAP_GFX;
 
+	if (!dmar_map_ipu)
+		iommu_identity_mapping |= IDENTMAP_IPU;
+
 	check_tylersburg_isoch();
 
 	ret = si_domain_init(hw_pass_through);
@@ -5607,6 +5621,18 @@  static void quirk_iommu_igfx(struct pci_dev *dev)
 	dmar_map_gfx = 0;
 }
 
+static void quirk_iommu_ipu(struct pci_dev *dev)
+{
+	if (!IS_INTEL_IPU(dev))
+		return;
+
+	if (risky_device(dev))
+		return;
+
+	pci_info(dev, "Passthrough IOMMU for integrated Intel IPU\n");
+	dmar_map_ipu = 0;
+}
+
 /* G4x/GM45 integrated gfx dmar support is totally busted. */
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx);
@@ -5642,6 +5668,9 @@  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
 
+/* disable IPU dmar support */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu);
+
 static void quirk_iommu_rwbf(struct pci_dev *dev)
 {
 	if (risky_device(dev))