@@ -1330,16 +1330,14 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
- if (intel_dp->use_max_params ||
- intel_dp->dpcd[DP_DPCD_REV] <= DP_DPCD_REV_11) {
+ if (intel_dp->use_max_params) {
/*
* Use the maximum clock and number of lanes the eDP panel
* advertizes being capable of in case the initial fast
- * optimal params failed us or the panel is DP 1.1 or earlier.
- * The panels are generally designed to support only a single
- * clock and lane configuration, and typically on older panels
- * these values correspond to the native resolution of the
- * panel.
+ * optimal params failed us. The panels are generally
+ * designed to support only a single clock and lane
+ * configuration, and typically on older panels these
+ * values correspond to the native resolution of the panel.
*/
limits.min_lane_count = limits.max_lane_count;
limits.min_clock = limits.max_clock;