From patchwork Fri Jul 9 19:08:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asmaa Mnebhi X-Patchwork-Id: 1503324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GM2l65MVzz9sWl; Sat, 10 Jul 2021 05:09:06 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1m1vru-0003Eo-T8; Fri, 09 Jul 2021 19:08:58 +0000 Received: from mail-il-dmz.mellanox.com ([193.47.165.129] helo=mellanox.co.il) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1m1vrn-00039T-67 for kernel-team@lists.ubuntu.com; Fri, 09 Jul 2021 19:08:51 +0000 Received: from Internal Mail-Server by MTLPINE1 (envelope-from asmaa@mellanox.com) with SMTP; 9 Jul 2021 22:08:49 +0300 Received: from farm-0002.mtbu.labs.mlnx (farm-0002.mtbu.labs.mlnx [10.15.2.32]) by mtbu-labmailer.labs.mlnx (8.14.4/8.14.4) with ESMTP id 169J8meC030208; Fri, 9 Jul 2021 15:08:48 -0400 Received: (from asmaa@localhost) by farm-0002.mtbu.labs.mlnx (8.14.7/8.13.8/Submit) id 169J8meL005460; Fri, 9 Jul 2021 15:08:48 -0400 From: Asmaa Mnebhi To: kernel-team@lists.ubuntu.com Subject: [SRU][F][PULL][PATCH v2 07/23] Revert "UBUNTU: SAUCE: mlxbf_gige_mdio.c: Support PHY interrupt on Bluesphere" Date: Fri, 9 Jul 2021 15:08:14 -0400 Message-Id: <20210709190830.5405-8-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210709190830.5405-1-asmaa@nvidia.com> References: <20210709190830.5405-1-asmaa@nvidia.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: asmaa@nvidia.com, davthompson@nvidia.com Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1934923 This reverts commit b418d3395a83a3e9c5c93bb44a07957ed5402904. Signed-off-by: Asmaa Mnebhi --- .../mellanox/mlxbf_gige/mlxbf_gige_main.c | 2 +- .../mellanox/mlxbf_gige/mlxbf_gige_mdio.c | 20 +++++++++---------- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c index 85a7ce19a6ff..ba6fd81d8fe6 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c @@ -21,7 +21,7 @@ #include "mlxbf_gige_regs.h" #define DRV_NAME "mlxbf_gige" -#define DRV_VERSION "1.10" +#define DRV_VERSION "1.9" static void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv, unsigned int index, u64 dmac) diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c index 636e19cf7050..dfe68aef9707 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c @@ -78,6 +78,10 @@ #define MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE 0x98 #define MLXBF_GIGE_GPIO12_BIT 12 +#define MLXBF_GIGE_CAUSE_OR_CAUSE_EVTEN0_MASK BIT(MLXBF_GIGE_GPIO12_BIT) +#define MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK BIT(MLXBF_GIGE_GPIO12_BIT) +#define MLXBF_GIGE_CAUSE_FALL_EN_MASK BIT(MLXBF_GIGE_GPIO12_BIT) +#define MLXBF_GIGE_CAUSE_OR_CLRCAUSE_MASK BIT(MLXBF_GIGE_GPIO12_BIT) static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add, int phy_reg, u32 opcode) @@ -156,7 +160,7 @@ static void mlxbf_gige_mdio_disable_phy_int(struct mlxbf_gige *priv) spin_lock_irqsave(&priv->gpio_lock, flags); val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0); - val &= ~priv->phy_int_gpio_mask; + val &= ~MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK; writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0); spin_unlock_irqrestore(&priv->gpio_lock, flags); } @@ -172,13 +176,13 @@ static void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv) * state goes low. */ val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_FALL_EN); - val |= priv->phy_int_gpio_mask; + val |= MLXBF_GIGE_CAUSE_FALL_EN_MASK; writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_FALL_EN); /* Enable PHY interrupt by setting the priority level */ val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0); - val |= priv->phy_int_gpio_mask; + val |= MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK; writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0); spin_unlock_irqrestore(&priv->gpio_lock, flags); @@ -201,7 +205,7 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id) */ val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_CAUSE_EVTEN0); - if (!(val & priv->phy_int_gpio_mask)) + if (!(val & MLXBF_GIGE_CAUSE_OR_CAUSE_EVTEN0_MASK)) return IRQ_NONE; phy_mac_interrupt(phydev); @@ -211,7 +215,7 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id) */ val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE); - val |= priv->phy_int_gpio_mask; + val |= MLXBF_GIGE_CAUSE_OR_CLRCAUSE_MASK; writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE); @@ -230,7 +234,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) { struct device *dev = &pdev->dev; struct resource *res; - u32 phy_int_gpio; int ret; res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_MDIO9); @@ -253,11 +256,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) writel(MLXBF_GIGE_MDIO_CFG_VAL, priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET); - ret = device_property_read_u32(dev, "phy-int-gpio", &phy_int_gpio); - if (ret < 0) - phy_int_gpio = MLXBF_GIGE_GPIO12_BIT; - priv->phy_int_gpio_mask = BIT(phy_int_gpio); - mlxbf_gige_mdio_enable_phy_int(priv); priv->mdiobus = devm_mdiobus_alloc(dev);