From patchwork Fri Jul 9 19:08:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asmaa Mnebhi X-Patchwork-Id: 1503332 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GM2lm2fDbz9sX2; Sat, 10 Jul 2021 05:09:40 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1m1vsV-0003fB-N1; Fri, 09 Jul 2021 19:09:35 +0000 Received: from mail-il-dmz.mellanox.com ([193.47.165.129] helo=mellanox.co.il) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1m1vrs-0003Cu-IS for kernel-team@lists.ubuntu.com; Fri, 09 Jul 2021 19:08:56 +0000 Received: from Internal Mail-Server by MTLPINE1 (envelope-from asmaa@mellanox.com) with SMTP; 9 Jul 2021 22:08:52 +0300 Received: from farm-0002.mtbu.labs.mlnx (farm-0002.mtbu.labs.mlnx [10.15.2.32]) by mtbu-labmailer.labs.mlnx (8.14.4/8.14.4) with ESMTP id 169J8pjW030220; Fri, 9 Jul 2021 15:08:51 -0400 Received: (from asmaa@localhost) by farm-0002.mtbu.labs.mlnx (8.14.7/8.13.8/Submit) id 169J8pjF005464; Fri, 9 Jul 2021 15:08:51 -0400 From: Asmaa Mnebhi To: kernel-team@lists.ubuntu.com Subject: [SRU][F][PULL][PATCH v2 11/23] Revert "UBUNTU: SAUCE: mlxbf-gige: remove gpio interrupt coalesce resources" Date: Fri, 9 Jul 2021 15:08:18 -0400 Message-Id: <20210709190830.5405-12-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210709190830.5405-1-asmaa@nvidia.com> References: <20210709190830.5405-1-asmaa@nvidia.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: asmaa@nvidia.com, davthompson@nvidia.com Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1934923 This reverts commit d11fc64e9e4bd09536448b4571660e1ad38a6a83. Signed-off-by: Asmaa Mnebhi --- .../ethernet/mellanox/mlxbf_gige/mlxbf_gige.h | 4 +++ .../mellanox/mlxbf_gige/mlxbf_gige_main.c | 2 +- .../mellanox/mlxbf_gige/mlxbf_gige_mdio.c | 34 +++++++++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h index 27786512d35f..63e07e60108d 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h @@ -75,6 +75,8 @@ struct mlxbf_gige { void __iomem *mdio_io; struct mii_bus *mdiobus; void __iomem *gpio_io; + void __iomem *cause_rsh_coalesce0_io; + void __iomem *cause_gpio_arm_coalesce0_io; u32 phy_int_gpio_mask; spinlock_t lock; spinlock_t gpio_lock; @@ -141,6 +143,8 @@ enum mlxbf_gige_res { MLXBF_GIGE_RES_MAC, MLXBF_GIGE_RES_MDIO9, MLXBF_GIGE_RES_GPIO0, + MLXBF_GIGE_RES_CAUSE_RSH_COALESCE0, + MLXBF_GIGE_RES_CAUSE_GPIO_ARM_COALESCE0, MLXBF_GIGE_RES_LLU, MLXBF_GIGE_RES_PLU }; diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c index 0a0e5ea76e66..a4ac1dc947d0 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c @@ -19,7 +19,7 @@ #include "mlxbf_gige_regs.h" #define DRV_NAME "mlxbf_gige" -#define DRV_VERSION "1.6" +#define DRV_VERSION "1.5" static void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv, unsigned int index, u64 dmac) diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c index 13e9af57fc77..464bfac9a650 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c @@ -71,6 +71,16 @@ FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \ FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13)) +/* The PHY interrupt line is shared with other interrupt lines such + * as GPIO and SMBus. So use YU registers to determine whether the + * interrupt comes from the PHY. + */ +#define MLXBF_GIGE_CAUSE_RSH_COALESCE0_GPIO_CAUSE_MASK 0x10 +#define MLXBF_GIGE_GPIO_CAUSE_IRQ_IS_SET(val) \ + ((val) & MLXBF_GIGE_CAUSE_RSH_COALESCE0_GPIO_CAUSE_MASK) + +#define MLXBF_GIGE_GPIO_BLOCK0_MASK BIT(0) + #define MLXBF_GIGE_GPIO_CAUSE_FALL_EN 0x48 #define MLXBF_GIGE_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x80 #define MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0 0x94 @@ -211,6 +221,10 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id) /* Clear interrupt when done, otherwise, no further interrupt * will be triggered. + * Writing 0x1 to the clear cause register also clears the + * following registers: + * cause_gpio_arm_coalesce0 + * cause_rsh_coalesce0 */ val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE); @@ -247,6 +261,26 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) if (!priv->gpio_io) return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, + MLXBF_GIGE_RES_CAUSE_RSH_COALESCE0); + if (!res) + return -ENODEV; + + priv->cause_rsh_coalesce0_io = + devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->cause_rsh_coalesce0_io) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, + MLXBF_GIGE_RES_CAUSE_GPIO_ARM_COALESCE0); + if (!res) + return -ENODEV; + + priv->cause_gpio_arm_coalesce0_io = + devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->cause_gpio_arm_coalesce0_io) + return -ENOMEM; + /* Configure mdio parameters */ writel(MLXBF_GIGE_MDIO_CFG_VAL, priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);