From patchwork Tue Mar 16 13:13:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kai-Heng Feng X-Patchwork-Id: 1453919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0DJ60Mx6z9sWV; Wed, 17 Mar 2021 00:13:42 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1lM9Vz-0003lF-Ev; Tue, 16 Mar 2021 13:13:39 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lM9Vv-0003kY-T9 for kernel-team@lists.ubuntu.com; Tue, 16 Mar 2021 13:13:35 +0000 Received: from 1-171-238-144.dynamic-ip.hinet.net ([1.171.238.144] helo=localhost) by youngberry.canonical.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lM9Vv-0000MC-2c for kernel-team@lists.ubuntu.com; Tue, 16 Mar 2021 13:13:35 +0000 From: Kai-Heng Feng To: kernel-team@lists.ubuntu.com Subject: [PATCH 1/1] UBUNTU: SAUCE: PCI: Serialize TGL e1000e PM ops Date: Tue, 16 Mar 2021 21:13:28 +0800 Message-Id: <20210316131328.1616280-2-kai.heng.feng@canonical.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210316131328.1616280-1-kai.heng.feng@canonical.com> References: <20210316131328.1616280-1-kai.heng.feng@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1919321 On TGL systems, PCI_COMMAND may randomly flip to 0 on system resume. This is devastating to drivers that use pci_set_master(), like NVMe and xHCI, to enable DMA in their resume routine, as pci_set_master() can inadvertently disable PCI_COMMAND_IO and PCI_COMMAND_MEMORY, making resources inaccessible. The issue is reproducible on all kernel releases, but obviously the situation is exacerbated by commit 6cecf02e77ab ('Revert "e1000e: disable s0ix entry and exit flows for ME systems"'). Seems like ME is out to lunch until it's finally out of ULP polling. So ensure e1000e PM ops are serialized by enforcing device links to workaround the issue. This is another hacky hackish hack that we can't upstream :) Of course this will make suspend and resume a bit slower, but at least we protect other PCI devices by keeping ME from going full basket case. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=212039 Signed-off-by: Kai-Heng Feng --- drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6c2c8dafccfd..fb13b3109a43 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5702,3 +5702,35 @@ static void pci_fixup_enable_vmd_nvme_ltr(struct pci_dev *pdev) } DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_EXPRESS, 0, pci_fixup_enable_vmd_nvme_ltr); + +static void pci_fixup_serialize_tgl_me_pm(struct pci_dev *pdev) +{ + struct pci_dev *rciep = NULL; + + if (!pdev->bus) + return; + + for_each_pci_dev(rciep) { + /* Most of TGL RCiEPs don't have type PCI_EXP_TYPE_RC_END, + * check parent bridge instead. */ + if (!rciep->bus) + continue; + + if (rciep->bus->self != pdev->bus->self) + continue; + + if (&rciep->dev == &pdev->dev) + continue; + + if (device_link_add(&rciep->dev, &pdev->dev, + DL_FLAG_STATELESS)) + pci_info(rciep, "Suspend before and resume after %s\n", + pci_name(pdev)); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15fb, pci_fixup_serialize_tgl_me_pm); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15fc, pci_fixup_serialize_tgl_me_pm); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15f9, pci_fixup_serialize_tgl_me_pm); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15fa, pci_fixup_serialize_tgl_me_pm); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15f4, pci_fixup_serialize_tgl_me_pm); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15f5, pci_fixup_serialize_tgl_me_pm);