| Message ID | 20210218123213.79158-2-stefan.bader@canonical.com |
|---|---|
| State | New |
| Headers | show |
| Series | Also fix Mellanox geneve offload on Focal | expand |
On 18.02.21 13:32, Stefan Bader wrote: > From: Moshe Shemesh <moshe@mellanox.com> > > BugLink: https://bugs.launchpad.net/bugs/1914447 > > In case WQE includes inline header the vlan is inserted by driver even > if vlan offload is set. On geneve over vlan interface where software > parser is used the SWP offsets should be updated according to the added > vlan. > > Fixes: e3cfc7e6b7bd ("net/mlx5e: TX, Add geneve tunnel stateless offload support") > Signed-off-by: Moshe Shemesh <moshe@mellanox.com> > Reviewed-by: Tariq Toukan <tariqt@nvidia.com> > Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> > > (backported from commit b544011f0e58ce43c40105468d6dc67f980a0c7a) > [smb: adjust for missing mlx5e_accel_tx_eseg(), mlx5e_txwqe_build_eseg() > mlx5e_tx_tunnel_accel() called directly from mlx5e_sq_xmit()] > Signed-off-by: Stefan Bader <stefan.bader@canonical.com> > Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> > Acked-by: Guilherme G. Piccoli <gpiccoli@canonical.com> > Signed-off-by: Kelsey Skunberg <kelsey.skunberg@canonical.com> > > (cherry picked from commit 8e382420abbba1b3e177b158f93d99d67a450d96 groovy) > Signed-off-by: Stefan Bader <stefan.bader@canonical.com> Given that it could be cleanly applied on 5.4 as well it seems relatively safe. Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> > --- > drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 9 +++++++++ > .../net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h | 4 +++- > drivers/net/ethernet/mellanox/mlx5/core/en_tx.c | 2 +- > 3 files changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h > index b6418823c63a..9277e0f059df 100644 > --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h > +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h > @@ -204,6 +204,15 @@ struct mlx5e_swp_spec { > u8 tun_l4_proto; > }; > > +static inline void mlx5e_eseg_swp_offsets_add_vlan(struct mlx5_wqe_eth_seg *eseg) > +{ > + /* SWP offsets are in 2-bytes words */ > + eseg->swp_outer_l3_offset += VLAN_HLEN / 2; > + eseg->swp_outer_l4_offset += VLAN_HLEN / 2; > + eseg->swp_inner_l3_offset += VLAN_HLEN / 2; > + eseg->swp_inner_l4_offset += VLAN_HLEN / 2; > +} > + > static inline void > mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, > struct mlx5e_swp_spec *swp_spec) > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h > index 3022463f2284..7246edb50f05 100644 > --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h > +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h > @@ -48,7 +48,7 @@ static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev) > } > > static inline void > -mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) > +mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, u16 ihs) > { > struct mlx5e_swp_spec swp_spec = {}; > unsigned int offset = 0; > @@ -82,6 +82,8 @@ mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) > } > > mlx5e_set_eseg_swp(skb, eseg, &swp_spec); > + if (skb_vlan_tag_present(skb) && ihs) > + mlx5e_eseg_swp_offsets_add_vlan(eseg); > } > > #else > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c > index d9e0fc146741..2317be1b9956 100644 > --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c > +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c > @@ -342,7 +342,7 @@ netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, > > #if IS_ENABLED(CONFIG_GENEVE) > if (skb->encapsulation) > - mlx5e_tx_tunnel_accel(skb, eseg); > + mlx5e_tx_tunnel_accel(skb, eseg, ihs); > #endif > mlx5e_txwqe_build_eseg_csum(sq, skb, eseg); > >
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h index b6418823c63a..9277e0f059df 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -204,6 +204,15 @@ struct mlx5e_swp_spec { u8 tun_l4_proto; }; +static inline void mlx5e_eseg_swp_offsets_add_vlan(struct mlx5_wqe_eth_seg *eseg) +{ + /* SWP offsets are in 2-bytes words */ + eseg->swp_outer_l3_offset += VLAN_HLEN / 2; + eseg->swp_outer_l4_offset += VLAN_HLEN / 2; + eseg->swp_inner_l3_offset += VLAN_HLEN / 2; + eseg->swp_inner_l4_offset += VLAN_HLEN / 2; +} + static inline void mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, struct mlx5e_swp_spec *swp_spec) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h index 3022463f2284..7246edb50f05 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h @@ -48,7 +48,7 @@ static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev) } static inline void -mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) +mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, u16 ihs) { struct mlx5e_swp_spec swp_spec = {}; unsigned int offset = 0; @@ -82,6 +82,8 @@ mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) } mlx5e_set_eseg_swp(skb, eseg, &swp_spec); + if (skb_vlan_tag_present(skb) && ihs) + mlx5e_eseg_swp_offsets_add_vlan(eseg); } #else diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c index d9e0fc146741..2317be1b9956 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -342,7 +342,7 @@ netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, #if IS_ENABLED(CONFIG_GENEVE) if (skb->encapsulation) - mlx5e_tx_tunnel_accel(skb, eseg); + mlx5e_tx_tunnel_accel(skb, eseg, ihs); #endif mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);