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[61.220.137.34]) by smtp.gmail.com with ESMTPSA id c13sm16645239pfp.147.2021.01.18.06.26.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 06:26:32 -0800 (PST) From: AceLan Kao To: kernel-team@lists.ubuntu.com Subject: [PATCH 10/10][SRU][OEM-5.10][Unstable] UBUNTU: SAUCE: drm/i915/gen9_bc : Add TGP PCH support Date: Mon, 18 Jan 2021 22:26:04 +0800 Message-Id: <20210118142604.207243-11-acelan.kao@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210118142604.207243-1-acelan.kao@canonical.com> References: <20210118142604.207243-1-acelan.kao@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.169; envelope-from=acelan@gmail.com; helo=mail-pf1-f169.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Tejas Upadhyay BugLink: https://bugs.launchpad.net/bugs/1909457 We have TGP PCH support for Tigerlake and Rocketlake. Similarly now TGP PCH can be used with Cometlake CPU. Changes since V3 : - Rebased to top drm-tip commit - dev_priv replaced with i915 for new API - Enable default Port B,C,D detection for TGP && GEN9_BC Changes since V2 : - IS_COMETLAKE replaced with IS_GEN9_BC - VBT ddc pin remapping added - Added dedicated HPD pin and DDC pin handling API Changes since V1 : - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Tejas Upadhyay (cherry picked from https://patchwork.freedesktop.org/patch/412664/) Signed-off-by: Chia-Lin Kao (AceLan) --- drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_pch.c | 3 ++- 5 files changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 973672489566..368079c451f6 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1605,6 +1605,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, }; +static const u8 gen9bc_tgp_ddc_pin_map[] = { + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { const u8 *ddc_pin_map; @@ -1615,6 +1621,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { + ddc_pin_map = gen9bc_tgp_ddc_pin_map; + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { ddc_pin_map = icp_ddc_pin_map; n_entries = ARRAY_SIZE(icp_ddc_pin_map); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index caad1fcb4096..f033d63768ac 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5071,7 +5071,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) { - if (port >= PORT_TC1) + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) + return HPD_PORT_TC1 + port - PORT_C; + else if (port >= PORT_TC1) return HPD_PORT_TC1 + port - PORT_TC1; else return HPD_PORT_A + port - PORT_A; @@ -5201,7 +5203,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); - else if (INTEL_GEN(dev_priv) >= 12) + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) && + HAS_PCH_TGP(dev_priv))) encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); else if (IS_JSL_EHL(dev_priv)) encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9c7a464dd3d6..97afa1fb515a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16958,7 +16958,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP * register */ - found = intel_de_read(dev_priv, SFUSE_STRAP); + if (HAS_PCH_TGP(dev_priv)) { + /* W/A due to lack of STRAP config on TGP PCH*/ + found = (SFUSE_STRAP_DDIB_DETECTED | + SFUSE_STRAP_DDIC_DETECTED | + SFUSE_STRAP_DDID_DETECTED); + } else { + found = intel_de_read(dev_priv, SFUSE_STRAP); + } if (found & SFUSE_STRAP_DDIB_DETECTED) intel_ddi_init(dev_priv, PORT_B); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 866bc6b4b73c..52eac30655b6 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3145,6 +3145,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return GMBUS_PIN_1_BXT + phy; } +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) +{ + enum phy phy = intel_port_to_phy(i915, port); + + drm_WARN_ON(&i915->drm, port == PORT_A); + + /* + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, + * final two outputs use type-c pins, even though they're actually + * combo outputs. With CMP, the traditional DDI A-D pins are used for + * all outputs. + */ + if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; + + return GMBUS_PIN_1_BXT + phy; +} + static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { return intel_port_to_phy(dev_priv, port) + 1; @@ -3191,6 +3209,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port); else if (HAS_PCH_MCC(dev_priv)) ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index f31c0dabd0cc..c1bc2d032360 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_TGP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && - !IS_ROCKETLAKE(dev_priv)); + !IS_ROCKETLAKE(dev_priv) && + !IS_GEN9_BC(dev_priv)); return PCH_TGP; case INTEL_PCH_JSP_DEVICE_ID_TYPE: case INTEL_PCH_JSP2_DEVICE_ID_TYPE: