diff mbox series

[16/38,SRU,G/H] drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link training

Message ID 20201124104313.421860-17-vicamo.yang@canonical.com
State New
Headers show
Series Add DRM support for LTTPR non-transparent link training mode | expand

Commit Message

You-Sheng Yang Nov. 24, 2020, 10:42 a.m. UTC 
From: Imre Deak <imre.deak@intel.com>

BugLink: https://bugs.launchpad.net/bugs/1903969

The value we program to DDI_BUF_CTL changes at the following places:
- At enabling/disabling the output to configure the port width etc, and
  to enable/disable the DDI BUF function.
- At the beginning/end of link re-training to disable/re-enable the DDI
  BUF function.
- On HSW/BDW/SKL to change the voltage swing/pre-emph levels.

Except of the above the value we program to the DDI_BUF_CTL register
(intel_dp->DP) doesn't change, so no need to reprogram the register when
changing the link training patterns (which is programmed via the
DP_TP_CTL register on DDI platforms).

v2:
- Fix the commit message wrt. voltage/pre-emph level values in
  intel_dp->DP. (Ville)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200714153141.10280-2-imre.deak@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit a5bcf8dde63142f36ae8ce720265d4c41a634d5c)
Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 ----
 1 file changed, 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3211fa6acf8c..94d91ff766b5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4035,7 +4035,6 @@  static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
-	enum port port = dp_to_dig_port(intel_dp)->base.port;
 	u32 temp;
 
 	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
@@ -4060,9 +4059,6 @@  static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 	}
 
 	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
-
-	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
-	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 }
 
 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)