From patchwork Tue Nov 24 09:12:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1405364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CgJGV4s1bz9sSs; Tue, 24 Nov 2020 20:13:22 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1khUNx-0005oV-HW; Tue, 24 Nov 2020 09:13:17 +0000 Received: from mail-pl1-f196.google.com ([209.85.214.196]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1khUNs-0005cQ-0j for kernel-team@lists.ubuntu.com; Tue, 24 Nov 2020 09:13:12 +0000 Received: by mail-pl1-f196.google.com with SMTP id l11so10393313plt.1 for ; Tue, 24 Nov 2020 01:13:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/TrFRL2WenVOhmCyWSZ816ulTGvu1GXxPOfrwTdFIH0=; b=Oeli/wPBXjIY7dkOhuqKSCVhwuCkqaa02K+/XiLkH5H5SyuCB6yaw/xrsoGJdOqEYI 3KK9kNBgRRzRHfohWcZ5HrDjrWGhtIASTHWCNDNSVruB6PKVW12ivg+N71ZzVxb63QTc RVdbnd84jBNEdsvA7Ty7rwTlOSninZ8nXSR5+yqeukEGX3o1zXhF3ltmqCJig/jCgBhV 2ht9vySNMVeZ1H/cm020ewUkkeIRiKQ5HYse+i/rQyCZmrkqg1udf8y1EhvVrncmvesN RhjFPuO4gCILDHmbSOs89ymlKEW9IjrYSSPVVC4iszRktrNSBwZVHN0SCaNoQgNLMWlq n34Q== X-Gm-Message-State: AOAM533ggsfXzPbqy9T9qvuhHkfEtLUe9HRqrbZSkhCMhZi+qAez9MXV r0NkmVNn/LUkqUU7l1Ksi8MUsX8V5hHhIQ== X-Google-Smtp-Source: ABdhPJx4RkgFfO81nUeFm/Mt1T8KxBG/jrwPVqAwERYhnbcQm8RgibZTeyj+Ku71UzPwGERfcFB5Ow== X-Received: by 2002:a17:902:7594:b029:d5:eda6:fb45 with SMTP id j20-20020a1709027594b02900d5eda6fb45mr3103676pll.5.1606209179901; Tue, 24 Nov 2020 01:12:59 -0800 (PST) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id y10sm2336600pjm.34.2020.11.24.01.12.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Nov 2020 01:12:59 -0800 (PST) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 11/15][SRU][U/OEM-5.10] UBUNTU: SAUCE: drm/i915: Simplify the link training functions Date: Tue, 24 Nov 2020 17:12:26 +0800 Message-Id: <20201124091230.335132-12-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201124091230.335132-1-vicamo.yang@canonical.com> References: <20201124091230.335132-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.196; envelope-from=vicamo@gmail.com; helo=mail-pl1-f196.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Imre Deak BugLink: https://bugs.launchpad.net/bugs/1903969 Split the prepare, link training, fallback-handling steps into their own functions for clarity and as a preparation for the upcoming LTTPR changes. While at it also: - Unexport and inline intel_dp_set_idle_link_train(), which is used at a single place. - Add some documentation to functions that are exported or that can use a better description about which part of the LT sequence they implement. v2: (Ville) - Unexport/inline intel_dp_set_idle_link_train() - Make the documentation of intel_dp_prepare_link_train()/intel_dp_stop_link_train() more accurate wrt. HW specific details. Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20201007170917.1764556-3-imre.deak@intel.com (cherry picked from commit 0a5991f5d022235ba085001e2a3926f83a0aed1b https://anongit.freedesktop.org/git/drm-tip.git) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_dp.c | 7 -- drivers/gpu/drm/i915/display/intel_dp.h | 2 - .../drm/i915/display/intel_dp_link_training.c | 100 ++++++++++++++---- 3 files changed, 79 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6f3c5595da34..986e992b215f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4519,13 +4519,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); } -void intel_dp_set_idle_link_train(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) -{ - if (intel_dp->set_idle_link_train) - intel_dp->set_idle_link_train(intel_dp, crtc_state); -} - static void intel_dp_link_down(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 22248f4ccae5..65d6b1b7b0f8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -96,8 +96,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, void intel_dp_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); -void intel_dp_set_idle_link_train(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select); bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index b2ff88a152cd..51d1316c37d5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -153,15 +153,15 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, return true; } -/* Enable corresponding port and start training pattern 1 */ +/* + * Prepare link training by configuring the link parameters. On DDI platforms + * also enable the port here. + */ static bool -intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +intel_dp_prepare_link_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - u8 voltage; - int voltage_tries, cr_tries, max_cr_tries; - bool max_vswing_reached = false; u8 link_config[2]; u8 link_bw, rate_select; @@ -196,6 +196,19 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, intel_dp->DP |= DP_PORT_EN; + return true; +} + +/* Perform the link training clock recovery phase using training pattern 1. */ +static bool +intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u8 voltage; + int voltage_tries, cr_tries, max_cr_tries; + bool max_vswing_reached = false; + /* clock recovery */ if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_TRAINING_PATTERN_1 | @@ -318,6 +331,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, return DP_TRAINING_PATTERN_2; } +/* + * Perform the link training channel equalization phase using one of training + * pattern 2, 3 or 4 depending on the source and sink capabilities. + */ static bool intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) @@ -383,12 +400,28 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, "Channel equalization failed 5 times\n"); } - intel_dp_set_idle_link_train(intel_dp, crtc_state); + if (intel_dp->set_idle_link_train) + intel_dp->set_idle_link_train(intel_dp, crtc_state); return channel_eq; - } +/** + * intel_dp_stop_link_train - stop link training + * @intel_dp: DP struct + * @crtc_state: state for CRTC attached to the encoder + * + * Stop the link training of the @intel_dp port, disabling the test pattern + * symbol generation on the port and disabling the training pattern in + * the sink's DPCD. + * + * What symbols are output on the port after this point is + * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern + * with the pipe being disabled, on older platforms it's HW specific if/how an + * idle pattern is generated, as the pipe is already enabled here for those. + * + * This function must be called after intel_dp_start_link_train(). + */ void intel_dp_stop_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -398,31 +431,39 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp, DP_TRAINING_PATTERN_DISABLE); } -void -intel_dp_start_link_train(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static bool +intel_dp_link_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct intel_connector *intel_connector = intel_dp->attached_connector; + bool ret = false; + + intel_dp_prepare_link_train(intel_dp, crtc_state); if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state)) - goto failure_handling; + goto out; + if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state)) - goto failure_handling; + goto out; - drm_dbg_kms(&dp_to_i915(intel_dp)->drm, - "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", - intel_connector->base.base.id, - intel_connector->base.name, - crtc_state->port_clock, crtc_state->lane_count); - return; + ret = true; - failure_handling: +out: drm_dbg_kms(&dp_to_i915(intel_dp)->drm, - "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", + "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d", intel_connector->base.base.id, intel_connector->base.name, + ret ? "passed" : "failed", crtc_state->port_clock, crtc_state->lane_count); + return ret; +} + +static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + if (intel_dp->hobl_active) { drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "Link Training failed with HOBL active, not enabling it from now on"); @@ -436,3 +477,20 @@ intel_dp_start_link_train(struct intel_dp *intel_dp, /* Schedule a Hotplug Uevent to userspace to start modeset */ schedule_work(&intel_connector->modeset_retry_work); } + +/** + * intel_dp_start_link_train - start link training + * @intel_dp: DP struct + * @crtc_state: state for CRTC attached to the encoder + * + * Start the link training of the @intel_dp port, scheduling a fallback + * retraining with reduced link rate/lane parameters if the link training + * fails. + * After calling this function intel_dp_stop_link_train() must be called. + */ +void intel_dp_start_link_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + if (!intel_dp_link_train(intel_dp, crtc_state)) + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); +}