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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id x16sm4692421pff.14.2020.10.29.23.02.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2020 23:02:58 -0700 (PDT) From: AceLan Kao To: kernel-team@lists.ubuntu.com Subject: [PATCH 11/23][SRU][OEM-5.6] platform/x86: intel_pmc_core: Add debugfs support to access live status registers Date: Fri, 30 Oct 2020 14:02:02 +0800 Message-Id: <20201030060214.780883-17-acelan.kao@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201030060214.780883-1-acelan.kao@canonical.com> References: <20201030060214.780883-1-acelan.kao@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.193; envelope-from=acelan@gmail.com; helo=mail-pf1-f193.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Gayatri Kammela BugLink: https://bugs.launchpad.net/bugs/1899883 Just like status registers, Tiger Lake has another set of 6 registers that help with status of the low power mode requirements. They are latched on every PC10 entry/exit and S0ix.y entry/exit as well. Though status and live status registers show the status of same list of requirements, live status registers show the status of the low power mode requirements at the time of reading. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko (cherry picked from commit 7adb1e8aeeb5d4d88012568b2049599c1a247cf2) Signed-off-by: AceLan Kao --- drivers/platform/x86/intel_pmc_core.c | 19 +++++++++++++++++++ drivers/platform/x86/intel_pmc_core.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 20950b3d49fa..d382e01f8173 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -570,6 +570,7 @@ static const struct pmc_reg_map tgl_reg_map = { .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET, .lpm_sts = tgl_lpm_maps, .lpm_status_offset = TGL_LPM_STATUS_OFFSET, + .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) @@ -1019,6 +1020,18 @@ static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs); +static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + const struct pmc_bit_map **maps = pmcdev->map->lpm_sts; + u32 offset = pmcdev->map->lpm_live_status_offset; + + pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs); + static int pmc_core_pkgc_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -1096,6 +1109,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_sts_regs_fops); } + + if (pmcdev->map->lpm_status_offset) { + debugfs_create_file("substate_live_status_registers", 0444, + pmcdev->dbgfs_dir, pmcdev, + &pmc_core_substate_l_sts_regs_fops); + } } #else static inline void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 3fdf4735c56f..1bbdffe80bde 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -196,6 +196,7 @@ enum ppfear_regs { /* Tigerlake Low Power Mode debug registers */ #define TGL_LPM_STATUS_OFFSET 0x1C3C +#define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C const char *lpm_modes[] = { "S0i2.0", @@ -257,6 +258,7 @@ struct pmc_reg_map { const u32 lpm_en_offset; const u32 lpm_residency_offset; const u32 lpm_status_offset; + const u32 lpm_live_status_offset; }; /**