From patchwork Wed Apr 22 06:55:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1274756 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 496WRL5cQSz9sSK; Wed, 22 Apr 2020 16:55:42 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1jR9II-0007dK-Am; Wed, 22 Apr 2020 06:55:38 +0000 Received: from mail-pf1-f194.google.com ([209.85.210.194]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jR9IE-0007ZL-VO for kernel-team@lists.ubuntu.com; Wed, 22 Apr 2020 06:55:35 +0000 Received: by mail-pf1-f194.google.com with SMTP id f7so596350pfa.9 for ; Tue, 21 Apr 2020 23:55:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wvc+BBqF1hsE3t5HS3RRPmCScVQudQoeKY5lxWoMaLw=; b=fBYuz1BdEpPKuP2VO6BpbUov9U75/3qJClVGfHuBatyIRDgjc4JWjle5JjBuxTIcCF MnlIkiicXPj10a+wwMHagl8Uem/OXRKqt/ZbKFbKtX87SzlqRSbTZRqJU0pp4lPp9T93 FrekP708bOL4eXSnz8e/ZAd7D+cCZVmhG8YQTcsntHgaBzM7tMaUA+84/5xUwZq5pNNh 1TZKMmedWis1oIHUEVQmkZgtYdlEy36bhBrM8Gf9I20hB6Zx8cyPYNmSyPiMcDakhKcf uDszPQEpi+unrO2oQdZx8p72ekmr3Nsxlf6EzWVFXZNdrOoSWoJhAFAFswKgAoYhYkdZ +60w== X-Gm-Message-State: AGi0PuYq7CqPf6L3I9MFEnrMLLZemm8+rRW+x7Fo0DnQXnzBb9gm8u1F 9UEhsG9dAWcO+wKm+rORJg6BtboiZGQ= X-Google-Smtp-Source: APiQypLJ9+VfH0mCB3pkDPBOug4/TnJ9ooOnprU1hevyZoB6+CIirVxRwGZNpwHOLJErP3i6jyK51w== X-Received: by 2002:a62:cdce:: with SMTP id o197mr1314964pfg.248.1587538532905; Tue, 21 Apr 2020 23:55:32 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id b140sm556108pfb.119.2020.04.21.23.55.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 23:55:32 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [SRU][F][PATCH 8/9] drm/i915/tc: Catch TC users accessing FIA registers without enable aux Date: Wed, 22 Apr 2020 14:55:09 +0800 Message-Id: <20200422065510.802065-9-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200422065510.802065-1-vicamo.yang@canonical.com> References: <20200422065510.802065-1-vicamo.yang@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: José Roberto de Souza BugLink: https://bugs.launchpad.net/bugs/1868936 As described in "drm/i915/tc/icl: Implement TC cold sequences" users of TC functions should held aux power well during access to avoid read garbage due HW in TC cold state. v3: - renamed is_tc_cold_blocked() to assert_tc_cold_blocked() - restored the removed 0xffffffff checks Reviewed-by: Imre Deak Tested-by: You-Sheng Yang Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20200414194956.164323-7-jose.souza@intel.com (backported from drm-tip commit 3ed347d1a73ea485ea9f68df64e95cc164e1a790) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_tc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index fa531c4914d8..dc42c406b09b 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -87,6 +87,20 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref) intel_display_power_put_async(i915, domain, wakeref); } +static void +assert_tc_cold_blocked(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + bool enabled; + + if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port) + return; + + enabled = intel_display_power_is_enabled(i915, + tc_cold_get_power_domain(dig_port)); + WARN_ON(!enabled); +} + u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -98,6 +112,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); WARN_ON(lane_mask == 0xffffffff); + assert_tc_cold_blocked(dig_port); return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >> DP_LANE_ASSIGNMENT_SHIFT(tc_port); @@ -112,6 +127,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) if (dig_port->tc_mode != TC_PORT_DP_ALT) return 4; + assert_tc_cold_blocked(dig_port); + lane_mask = 0; with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) lane_mask = intel_tc_port_get_lane_mask(dig_port); @@ -144,6 +161,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); + assert_tc_cold_blocked(dig_port); + val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);