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[SRU,Xenial,3/4] UBUNTU: SAUCE: x86: Move hunks and sync to upstream stable 4.9

Message ID 20190401132907.24823-4-juergh@canonical.com
State New
Headers show
Series Xenial: Sync to upstream v4.9 (LP: #1820872) | expand

Commit Message

Juerg Haefliger April 1, 2019, 1:29 p.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/1820872

Trivial changes to reduce the delta between Xenial 4.4 and upstream
stable 4.9 so that future cherry-picking results in fewer conflicts.

Signed-off-by: Juerg Haefliger <juergh@canonical.com>
---
 arch/x86/include/asm/nospec-branch.h | 7 ++++---
 arch/x86/kernel/cpu/amd.c            | 4 +---
 arch/x86/kernel/cpu/bugs.c           | 3 +--
 3 files changed, 6 insertions(+), 8 deletions(-)
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Patch

diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
index a6120d43caa7..46eb80b1b57b 100644
--- a/arch/x86/include/asm/nospec-branch.h
+++ b/arch/x86/include/asm/nospec-branch.h
@@ -202,9 +202,6 @@  enum spectre_v2_mitigation {
 	SPECTRE_V2_IBRS_ENHANCED,
 };
 
-/* The Intel SPEC CTRL MSR base value cache */
-extern u64 x86_spec_ctrl_base;
-
 /* The Speculative Store Bypass disable variants */
 enum ssb_mitigation {
 	SPEC_STORE_BYPASS_NONE,
@@ -256,6 +253,9 @@  static inline void indirect_branch_prediction_barrier(void)
 				      X86_FEATURE_USE_IBPB);
 }
 
+/* The Intel SPEC CTRL MSR base value cache */
+extern u64 x86_spec_ctrl_base;
+
 /*
  * With retpoline, we must use IBRS to restrict branch prediction
  * before calling into firmware.
@@ -265,6 +265,7 @@  static inline void indirect_branch_prediction_barrier(void)
 #define firmware_restrict_branch_speculation_start()			\
 do {									\
 	u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;			\
+									\
 	preempt_disable();						\
 	alternative_msr_write(MSR_IA32_SPEC_CTRL, val,			\
 			      X86_FEATURE_USE_IBRS_FW);			\
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 081732f8a598..b3f68f9500cc 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -296,10 +296,8 @@  static int nearby_node(int apicid)
 
 static void amd_get_topology_early(struct cpuinfo_x86 *c)
 {
-#ifdef CONFIG_SMP
-	if (boot_cpu_has(X86_FEATURE_TOPOEXT))
+	if (cpu_has(c, X86_FEATURE_TOPOEXT))
 		smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0x3) + 1;
-#endif
 }
 
 /*
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 63d5b84e680b..4759c11b2380 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -396,7 +396,7 @@  retpoline_auto:
 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 	retpoline_amd:
 		if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
-			pr_err("Spectre mitigation: LFENCE not serializing. Switching to generic retpoline\n");
+			pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 			goto retpoline_generic;
 		}
 		mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
@@ -860,7 +860,6 @@  static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
 
 	case X86_BUG_SPECTRE_V1:
 		return sprintf(buf, "Mitigation: __user pointer sanitization\n");
-		break;
 
 	case X86_BUG_SPECTRE_V2:
 		return sprintf(buf, "%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],