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[2/4,Bionic] Revert "UBUNTU: SAUCE: scsi: hisi_sas: config for hip08 ES"

Message ID 20180412164412.9146-3-dann.frazier@canonical.com
State New
Headers show
Series hisi_sas: Revert and replace SAUCE patches w/ upstream | expand

Commit Message

dann frazier April 12, 2018, 4:44 p.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/1762824

Replacing with upstream version.

This reverts commit 3aa67d68ce5c0041634e954ee8a4ec611b9b256d.

Signed-off-by: dann frazier <dann.frazier@canonical.com>
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 42 ++++++++------------------
 1 file changed, 13 insertions(+), 29 deletions(-)
diff mbox series

Patch

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 1d536a7a1247..a1f18689729a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -172,7 +172,6 @@ 
 #define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
 #define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
 #define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
-#define SAS_RX_TRAIN_TIMER		(PORT_BASE + 0x2a4)
 #define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
 #define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
 #define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
@@ -185,17 +184,6 @@ 
 #define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
 #define DMA_RX_STATUS_BUSY_OFF		0
 #define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)
-
-#define COARSETUNE_TIME			(PORT_BASE + 0x304)
-#define SAS_TXDEEMPH_G1			(PORT_BASE + 0x350)
-#define SAS_TXDEEMPH_G2			(PORT_BASE + 0x354)
-#define SAS_TXDEEMPH_G3			(PORT_BASE + 0x358)
-#define SAS_TXDEEMPH_G4			(PORT_BASE + 0x35c)
-#define SATA_TXDEEMPH_G1			(PORT_BASE + 0x360)
-#define SATA_TXDEEMPH_G2			(PORT_BASE + 0x364)
-#define SATA_TXDEEMPH_G3			(PORT_BASE + 0x368)
-#define SATA_TXDEEMPH_G4			(PORT_BASE + 0x36c)
-
 #define ERR_CNT_DWS_LOST		(PORT_BASE + 0x380)
 #define ERR_CNT_RESET_PROB		(PORT_BASE + 0x384)
 #define ERR_CNT_INVLD_DW		(PORT_BASE + 0x390)
@@ -414,6 +402,7 @@  static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 			 (u32)((1ULL << hisi_hba->queue_count) - 1));
 	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
 	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
+	hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
 	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
@@ -434,10 +423,10 @@  static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 
 	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
+	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
 
 	for (i = 0; i < hisi_hba->n_phy; i++) {
-		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
-		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
+		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
@@ -449,21 +438,16 @@  static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
-		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
-
-		/* used for 12G negotiate */
-		hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
-		hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G1, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G2, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G3, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G4, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G1, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G2, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G3, 0x8d04);
-		hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G4, 0x8d04);
-
-		/* disable stp link timer */
-		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x2710);
+		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
+		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
+		hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
+				     0xa03e8);
+		hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
+				     0xa03e8);
+		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
+				     0x7f7a120);
+		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER,
+				     0x2a0a80);
 	}
 	for (i = 0; i < hisi_hba->queue_count; i++) {
 		/* Delivery queue */