[08/28] net: aquantia: Fix register definitions to linux style

Message ID	20180329100643.27299-9-kai.heng.feng@canonical.com
State	New
Headers	show Return-Path: <kernel-team-bounces@lists.ubuntu.com> From: Kai-Heng Feng <kai.heng.feng@canonical.com> To: kernel-team@lists.ubuntu.com Subject: [PATCH 08/28] net: aquantia: Fix register definitions to linux style Date: Thu, 29 Mar 2018 18:06:23 +0800 Message-Id: <20180329100643.27299-9-kai.heng.feng@canonical.com> In-Reply-To: <20180329100643.27299-1-kai.heng.feng@canonical.com> References: <20180329100643.27299-1-kai.heng.feng@canonical.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" <kernel-team-bounces@lists.ubuntu.com>
Series	[01/28] net: aquantia: Eliminate AQ_DIMOF, replace with ARRAY_SIZE \| expand [01/28] net: aquantia: Eliminate AQ_DIMOF, replace with ARRAY_SIZE [02/28] net: aquantia: Cleanup status flags accesses [03/28] net: aquantia: Cleanup hardware access modules [04/28] net: aquantia: Remove duplicate hardware descriptors declarations [05/28] net: aquantia: Add const qualifiers for hardware ops tables [06/28] net: aquantia: Simplify dependencies between pci modules [07/28] net: aquantia: Eliminate aq_nic structure abstraction [08/28] net: aquantia: Fix register definitions to linux style [09/28] net: aquantia: Prepend hw access functions declarations with prefix [10/28] net: aquantia: Fix internal stats calculation on rx [11/28] net: aquantia: Introduce new device ids and constants [12/28] net: aquantia: Introduce new AQC devices and capabilities [13/28] net: aquantia: Convert hw and caps structures to const static pointers [14/28] net: aquantia: Cleanup pci functions module [15/28] net: aquantia: Remove create/destroy from hw ops [16/28] net: aquantia: Change confusing no_ff_addr to more meaningful name [17/28] net: aquantia: Introduce firmware ops callbacks [18/28] net: aquantia: Introduce support for new firmware on AQC cards [19/28] net: aquantia: Introduce global AQC hardware reset sequence [20/28] net: aquantia: Report correct mediatype via ethtool [21/28] net: aquantia: bump driver version to match aquantia internal numbering [22/28] net: aquantia: Fix hardware reset when SPI may rarely hangup [23/28] net: aquantia: Fix a regression with reset on old firmware [24/28] net: aquantia: Change inefficient wait loop on fw data reads [25/28] net: aquantia: Add tx clean budget and valid budget handling logic [26/28] net: aquantia: Allow live mac address changes [27/28] net: aquantia: Implement pci shutdown callback [28/28] net: aquantia: driver version bump

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index 9b7e04f536ff..79e59b73992f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -381,14 +381,15 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr) hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); /* Force limit MRRS on RDM/TDM to 2K */ - val = aq_hw_read_reg(self, pci_reg_control6_adr); - aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404); + val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR); + aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR, + (val & ~0x707) | 0x404); /* TX DMA total request limit. B0 hardware is not capable to * handle more than (8K-MRRS) incoming DMA data. * Value 24 in 256byte units */ - aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24); + aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24); /* Reset link status and read out initial hardware counters */ self->aq_link_status.mbps = 0; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c index 3de651afa8c7..2f21fe6fd6ba 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c @@ -18,95 +18,96 @@ /* global */ void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, u32 semaphore) { - aq_hw_write_reg(aq_hw, glb_cpu_sem_adr(semaphore), glb_cpu_sem); + aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem); } u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore) { - return aq_hw_read_reg(aq_hw, glb_cpu_sem_adr(semaphore)); + return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore)); } void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis) { - aq_hw_write_reg_bit(aq_hw, glb_reg_res_dis_adr, - glb_reg_res_dis_msk, - glb_reg_res_dis_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR, + HW_ATL_GLB_REG_RES_DIS_MSK, + HW_ATL_GLB_REG_RES_DIS_SHIFT, glb_reg_res_dis); } void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res) { - aq_hw_write_reg_bit(aq_hw, glb_soft_res_adr, glb_soft_res_msk, - glb_soft_res_shift, soft_res); + aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, + HW_ATL_GLB_SOFT_RES_MSK, + HW_ATL_GLB_SOFT_RES_SHIFT, soft_res); } u32 glb_soft_res_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg_bit(aq_hw, glb_soft_res_adr, - glb_soft_res_msk, - glb_soft_res_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, + HW_ATL_GLB_SOFT_RES_MSK, + HW_ATL_GLB_SOFT_RES_SHIFT); } u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, rx_dma_stat_counter7_adr); + return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR); } u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, glb_mif_id_adr); + return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR); } /* stats */ u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, rpb_rx_dma_drop_pkt_cnt_adr); + return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR); } u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_counterlsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW); } u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_counterlsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW); } u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_counterlsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW); } u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_counterlsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW); } u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_countermsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW); } u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_countermsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW); } u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_countermsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW); } u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_countermsw__adr); + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW); } /* interrupt */ void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw) { - aq_hw_write_reg(aq_hw, itr_iamrlsw_adr, irq_auto_masklsw); + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw); } void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx) @@ -114,13 +115,13 @@ void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx) /* register address for bitfield imr_rx{r}_en */ static u32 itr_imr_rxren_adr[32] = { 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, - 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, - 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, - 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, - 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU }; /* bitmask for bitfield imr_rx{r}_en */ @@ -154,13 +155,13 @@ void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx) /* register address for bitfield imr_tx{t}_en */ static u32 itr_imr_txten_adr[32] = { 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, - 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, - 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, - 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, - 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU }; /* bitmask for bitfield imr_tx{t}_en */ @@ -194,25 +195,25 @@ void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx) /* register address for bitfield imr_rx{r}[4:0] */ static u32 itr_imr_rxr_adr[32] = { 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, - 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, - 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, - 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, - 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU }; /* bitmask for bitfield imr_rx{r}[4:0] */ static u32 itr_imr_rxr_msk[32] = { - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, - 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU }; /* lower bit position of bitfield imr_rx{r}[4:0] */ @@ -234,25 +235,25 @@ void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx) /* register address for bitfield imr_tx{t}[4:0] */ static u32 itr_imr_txt_adr[32] = { 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, - 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, - 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, - 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, - 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU }; /* bitmask for bitfield imr_tx{t}[4:0] */ static u32 itr_imr_txt_msk[32] = { - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, - 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U }; /* lower bit position of bitfield imr_tx{t}[4:0] */ @@ -271,185 +272,189 @@ void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx) void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw) { - aq_hw_write_reg(aq_hw, itr_imcrlsw_adr, irq_msk_clearlsw); + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw); } void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw) { - aq_hw_write_reg(aq_hw, itr_imsrlsw_adr, irq_msk_setlsw); + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw); } void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis) { - aq_hw_write_reg_bit(aq_hw, itr_reg_res_dsbl_adr, - itr_reg_res_dsbl_msk, - itr_reg_res_dsbl_shift, irq_reg_res_dis); + aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR, + HW_ATL_ITR_REG_RES_DSBL_MSK, + HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis); } void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_status_clearlsw) { - aq_hw_write_reg(aq_hw, itr_iscrlsw_adr, irq_status_clearlsw); + aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw); } u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, itr_isrlsw_adr); + return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR); } u32 itr_res_irq_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg_bit(aq_hw, itr_res_adr, itr_res_msk, - itr_res_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, + HW_ATL_ITR_RES_SHIFT); } void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq) { - aq_hw_write_reg_bit(aq_hw, itr_res_adr, itr_res_msk, - itr_res_shift, res_irq); + aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, + HW_ATL_ITR_RES_SHIFT, res_irq); } /* rdm */ void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) { - aq_hw_write_reg_bit(aq_hw, rdm_dcadcpuid_adr(dca), - rdm_dcadcpuid_msk, - rdm_dcadcpuid_shift, cpuid); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca), + HW_ATL_RDM_DCADCPUID_MSK, + HW_ATL_RDM_DCADCPUID_SHIFT, cpuid); } void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en) { - aq_hw_write_reg_bit(aq_hw, rdm_dca_en_adr, rdm_dca_en_msk, - rdm_dca_en_shift, rx_dca_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK, + HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en); } void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode) { - aq_hw_write_reg_bit(aq_hw, rdm_dca_mode_adr, rdm_dca_mode_msk, - rdm_dca_mode_shift, rx_dca_mode); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR, + HW_ATL_RDM_DCA_MODE_MSK, + HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode); } void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, u32 rx_desc_data_buff_size, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rdm_descddata_size_adr(descriptor), - rdm_descddata_size_msk, - rdm_descddata_size_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor), + HW_ATL_RDM_DESCDDATA_SIZE_MSK, + HW_ATL_RDM_DESCDDATA_SIZE_SHIFT, rx_desc_data_buff_size); } void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, u32 dca) { - aq_hw_write_reg_bit(aq_hw, rdm_dcaddesc_en_adr(dca), - rdm_dcaddesc_en_msk, - rdm_dcaddesc_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca), + HW_ATL_RDM_DCADDESC_EN_MSK, + HW_ATL_RDM_DCADDESC_EN_SHIFT, rx_desc_dca_en); } void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rdm_descden_adr(descriptor), - rdm_descden_msk, - rdm_descden_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor), + HW_ATL_RDM_DESCDEN_MSK, + HW_ATL_RDM_DESCDEN_SHIFT, rx_desc_en); } void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, u32 rx_desc_head_buff_size, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_size_adr(descriptor), - rdm_descdhdr_size_msk, - rdm_descdhdr_size_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor), + HW_ATL_RDM_DESCDHDR_SIZE_MSK, + HW_ATL_RDM_DESCDHDR_SIZE_SHIFT, rx_desc_head_buff_size); } void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, u32 rx_desc_head_splitting, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_split_adr(descriptor), - rdm_descdhdr_split_msk, - rdm_descdhdr_split_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor), + HW_ATL_RDM_DESCDHDR_SPLIT_MSK, + HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT, rx_desc_head_splitting); } u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) { - return aq_hw_read_reg_bit(aq_hw, rdm_descdhd_adr(descriptor), - rdm_descdhd_msk, rdm_descdhd_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor), + HW_ATL_RDM_DESCDHD_MSK, + HW_ATL_RDM_DESCDHD_SHIFT); } void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rdm_descdlen_adr(descriptor), - rdm_descdlen_msk, rdm_descdlen_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor), + HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT, rx_desc_len); } void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rdm_descdreset_adr(descriptor), - rdm_descdreset_msk, rdm_descdreset_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor), + HW_ATL_RDM_DESCDRESET_MSK, + HW_ATL_RDM_DESCDRESET_SHIFT, rx_desc_res); } void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_wr_wb_irq_en) { - aq_hw_write_reg_bit(aq_hw, rdm_int_desc_wrb_en_adr, - rdm_int_desc_wrb_en_msk, - rdm_int_desc_wrb_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR, + HW_ATL_RDM_INT_DESC_WRB_EN_MSK, + HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT, rx_desc_wr_wb_irq_en); } void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, u32 dca) { - aq_hw_write_reg_bit(aq_hw, rdm_dcadhdr_en_adr(dca), - rdm_dcadhdr_en_msk, - rdm_dcadhdr_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca), + HW_ATL_RDM_DCADHDR_EN_MSK, + HW_ATL_RDM_DCADHDR_EN_SHIFT, rx_head_dca_en); } void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca) { - aq_hw_write_reg_bit(aq_hw, rdm_dcadpay_en_adr(dca), - rdm_dcadpay_en_msk, rdm_dcadpay_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca), + HW_ATL_RDM_DCADPAY_EN_MSK, + HW_ATL_RDM_DCADPAY_EN_SHIFT, rx_pld_dca_en); } void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en) { - aq_hw_write_reg_bit(aq_hw, rdm_int_rim_en_adr, - rdm_int_rim_en_msk, - rdm_int_rim_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR, + HW_ATL_RDM_INT_RIM_EN_MSK, + HW_ATL_RDM_INT_RIM_EN_SHIFT, rdm_intr_moder_en); } /* reg */ void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx) { - aq_hw_write_reg(aq_hw, gen_intr_map_adr(regidx), gen_intr_map); + aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map); } u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, gen_intr_stat_adr); + return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR); } void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl) { - aq_hw_write_reg(aq_hw, intr_glb_ctl_adr, intr_glb_ctl); + aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl); } void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle) { - aq_hw_write_reg(aq_hw, intr_thr_adr(throttle), intr_thr); + aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr); } void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, u32 rx_dma_desc_base_addrlsw, u32 descriptor) { - aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor), + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), rx_dma_desc_base_addrlsw); } @@ -457,61 +462,64 @@ void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, u32 rx_dma_desc_base_addrmsw, u32 descriptor) { - aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor), + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), rx_dma_desc_base_addrmsw); } u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor) { - return aq_hw_read_reg(aq_hw, rx_dma_desc_stat_adr(descriptor)); + return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor)); } void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, u32 rx_dma_desc_tail_ptr, u32 descriptor) { - aq_hw_write_reg(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor), + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor), rx_dma_desc_tail_ptr); } void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr_msk) { - aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_msk_adr, rx_flr_mcst_flr_msk); + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR, + rx_flr_mcst_flr_msk); } void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, u32 filter) { - aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_adr(filter), rx_flr_mcst_flr); + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter), + rx_flr_mcst_flr); } void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, u32 rx_flr_rss_control1) { - aq_hw_write_reg(aq_hw, rx_flr_rss_control1_adr, rx_flr_rss_control1); + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR, + rx_flr_rss_control1); } void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_filter_control2) { - aq_hw_write_reg(aq_hw, rx_flr_control2_adr, rx_filter_control2); + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2); } void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, u32 rx_intr_moderation_ctl, u32 queue) { - aq_hw_write_reg(aq_hw, rx_intr_moderation_ctl_adr(queue), + aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue), rx_intr_moderation_ctl); } void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl) { - aq_hw_write_reg(aq_hw, tx_dma_debug_ctl_adr, tx_dma_debug_ctl); + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl); } void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, u32 tx_dma_desc_base_addrlsw, u32 descriptor) { - aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor), + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), tx_dma_desc_base_addrlsw); } @@ -519,14 +527,14 @@ void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, u32 tx_dma_desc_base_addrmsw, u32 descriptor) { - aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor), + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), tx_dma_desc_base_addrmsw); } void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, u32 tx_dma_desc_tail_ptr, u32 descriptor) { - aq_hw_write_reg(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor), + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor), tx_dma_desc_tail_ptr); } @@ -534,39 +542,41 @@ void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, u32 tx_intr_moderation_ctl, u32 queue) { - aq_hw_write_reg(aq_hw, tx_intr_moderation_ctl_adr(queue), + aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue), tx_intr_moderation_ctl); } /* RPB: rx packet buffer */ void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk) { - aq_hw_write_reg_bit(aq_hw, rpb_dma_sys_lbk_adr, - rpb_dma_sys_lbk_msk, - rpb_dma_sys_lbk_shift, dma_sys_lbk); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR, + HW_ATL_RPB_DMA_SYS_LBK_MSK, + HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk); } void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, u32 rx_traf_class_mode) { - aq_hw_write_reg_bit(aq_hw, rpb_rpf_rx_tc_mode_adr, - rpb_rpf_rx_tc_mode_msk, - rpb_rpf_rx_tc_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, + HW_ATL_RPB_RPF_RX_TC_MODE_MSK, + HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT, rx_traf_class_mode); } void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en) { - aq_hw_write_reg_bit(aq_hw, rpb_rx_buf_en_adr, rpb_rx_buf_en_msk, - rpb_rx_buf_en_shift, rx_buff_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR, + HW_ATL_RPB_RX_BUF_EN_MSK, + HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en); } void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_buff_hi_threshold_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, rpb_rxbhi_thresh_adr(buffer), - rpb_rxbhi_thresh_msk, rpb_rxbhi_thresh_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer), + HW_ATL_RPB_RXBHI_THRESH_MSK, + HW_ATL_RPB_RXBHI_THRESH_SHIFT, rx_buff_hi_threshold_per_tc); } @@ -574,32 +584,34 @@ void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_buff_lo_threshold_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, rpb_rxblo_thresh_adr(buffer), - rpb_rxblo_thresh_msk, - rpb_rxblo_thresh_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer), + HW_ATL_RPB_RXBLO_THRESH_MSK, + HW_ATL_RPB_RXBLO_THRESH_SHIFT, rx_buff_lo_threshold_per_tc); } void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode) { - aq_hw_write_reg_bit(aq_hw, rpb_rx_fc_mode_adr, - rpb_rx_fc_mode_msk, - rpb_rx_fc_mode_shift, rx_flow_ctl_mode); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR, + HW_ATL_RPB_RX_FC_MODE_MSK, + HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode); } void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_pkt_buff_size_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, rpb_rxbbuf_size_adr(buffer), - rpb_rxbbuf_size_msk, rpb_rxbbuf_size_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer), + HW_ATL_RPB_RXBBUF_SIZE_MSK, + HW_ATL_RPB_RXBBUF_SIZE_SHIFT, rx_pkt_buff_size_per_tc); } void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, rpb_rxbxoff_en_adr(buffer), - rpb_rxbxoff_en_msk, rpb_rxbxoff_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer), + HW_ATL_RPB_RXBXOFF_EN_MSK, + HW_ATL_RPB_RXBXOFF_EN_SHIFT, rx_xoff_en_per_tc); } @@ -608,62 +620,63 @@ void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc, void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, u32 l2broadcast_count_threshold) { - aq_hw_write_reg_bit(aq_hw, rpfl2bc_thresh_adr, - rpfl2bc_thresh_msk, - rpfl2bc_thresh_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR, + HW_ATL_RPFL2BC_THRESH_MSK, + HW_ATL_RPFL2BC_THRESH_SHIFT, l2broadcast_count_threshold); } void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en) { - aq_hw_write_reg_bit(aq_hw, rpfl2bc_en_adr, rpfl2bc_en_msk, - rpfl2bc_en_shift, l2broadcast_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK, + HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en); } void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2broadcast_flr_act) { - aq_hw_write_reg_bit(aq_hw, rpfl2bc_act_adr, rpfl2bc_act_msk, - rpfl2bc_act_shift, l2broadcast_flr_act); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR, + HW_ATL_RPFL2BC_ACT_MSK, + HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act); } void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpfl2mc_enf_adr(filter), - rpfl2mc_enf_msk, - rpfl2mc_enf_shift, l2multicast_flr_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter), + HW_ATL_RPFL2MC_ENF_MSK, + HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en); } void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, u32 l2promiscuous_mode_en) { - aq_hw_write_reg_bit(aq_hw, rpfl2promis_mode_adr, - rpfl2promis_mode_msk, - rpfl2promis_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR, + HW_ATL_RPFL2PROMIS_MODE_MSK, + HW_ATL_RPFL2PROMIS_MODE_SHIFT, l2promiscuous_mode_en); } void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpfl2uc_actf_adr(filter), - rpfl2uc_actf_msk, rpfl2uc_actf_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter), + HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT, l2unicast_flr_act); } void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpfl2uc_enf_adr(filter), - rpfl2uc_enf_msk, - rpfl2uc_enf_shift, l2unicast_flr_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter), + HW_ATL_RPFL2UC_ENF_MSK, + HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en); } void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, u32 l2unicast_dest_addresslsw, u32 filter) { - aq_hw_write_reg(aq_hw, rpfl2uc_daflsw_adr(filter), + aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter), l2unicast_dest_addresslsw); } @@ -671,17 +684,18 @@ void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, u32 l2unicast_dest_addressmsw, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpfl2uc_dafmsw_adr(filter), - rpfl2uc_dafmsw_msk, rpfl2uc_dafmsw_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter), + HW_ATL_RPFL2UC_DAFMSW_MSK, + HW_ATL_RPFL2UC_DAFMSW_SHIFT, l2unicast_dest_addressmsw); } void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, u32 l2_accept_all_mc_packets) { - aq_hw_write_reg_bit(aq_hw, rpfl2mc_accept_all_adr, - rpfl2mc_accept_all_msk, - rpfl2mc_accept_all_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR, + HW_ATL_RPFL2MC_ACCEPT_ALL_MSK, + HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT, l2_accept_all_mc_packets); } @@ -690,8 +704,8 @@ void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, { /* register address for bitfield rx_tc_up{t}[2:0] */ static u32 rpf_rpb_rx_tc_upt_adr[8] = { - 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U, - 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U + 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U, + 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U }; /* bitmask for bitfield rx_tc_up{t}[2:0] */ @@ -713,266 +727,270 @@ void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr) { - aq_hw_write_reg_bit(aq_hw, rpf_rss_key_addr_adr, - rpf_rss_key_addr_msk, - rpf_rss_key_addr_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR, + HW_ATL_RPF_RSS_KEY_ADDR_MSK, + HW_ATL_RPF_RSS_KEY_ADDR_SHIFT, rss_key_addr); } void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data) { - aq_hw_write_reg(aq_hw, rpf_rss_key_wr_data_adr, + aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR, rss_key_wr_data); } u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr, - rpf_rss_key_wr_eni_msk, - rpf_rss_key_wr_eni_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, + HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, + HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT); } void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en) { - aq_hw_write_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr, - rpf_rss_key_wr_eni_msk, - rpf_rss_key_wr_eni_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, + HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, + HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT, rss_key_wr_en); } void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_addr) { - aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_addr_adr, - rpf_rss_redir_addr_msk, - rpf_rss_redir_addr_shift, rss_redir_tbl_addr); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR, + HW_ATL_RPF_RSS_REDIR_ADDR_MSK, + HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT, + rss_redir_tbl_addr); } void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_wr_data) { - aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_data_adr, - rpf_rss_redir_wr_data_msk, - rpf_rss_redir_wr_data_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR, + HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK, + HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT, rss_redir_tbl_wr_data); } u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr, - rpf_rss_redir_wr_eni_msk, - rpf_rss_redir_wr_eni_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, + HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, + HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT); } void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en) { - aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr, - rpf_rss_redir_wr_eni_msk, - rpf_rss_redir_wr_eni_shift, rss_redir_wr_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, + HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, + HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en); } void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, u32 tpo_to_rpf_sys_lbk) { - aq_hw_write_reg_bit(aq_hw, rpf_tpo_rpf_sys_lbk_adr, - rpf_tpo_rpf_sys_lbk_msk, - rpf_tpo_rpf_sys_lbk_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR, + HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK, + HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT, tpo_to_rpf_sys_lbk); } void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_inner_tpid_adr, - rpf_vl_inner_tpid_msk, - rpf_vl_inner_tpid_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR, + HW_ATL_RPF_VL_INNER_TPID_MSK, + HW_ATL_RPF_VL_INNER_TPID_SHIFT, vlan_inner_etht); } void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_outer_tpid_adr, - rpf_vl_outer_tpid_msk, - rpf_vl_outer_tpid_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR, + HW_ATL_RPF_VL_OUTER_TPID_MSK, + HW_ATL_RPF_VL_OUTER_TPID_SHIFT, vlan_outer_etht); } void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_promis_mode_adr, - rpf_vl_promis_mode_msk, - rpf_vl_promis_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, + HW_ATL_RPF_VL_PROMIS_MODE_MSK, + HW_ATL_RPF_VL_PROMIS_MODE_SHIFT, vlan_prom_mode_en); } void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, u32 vlan_accept_untagged_packets) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_accept_untagged_mode_adr, - rpf_vl_accept_untagged_mode_msk, - rpf_vl_accept_untagged_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR, + HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK, + HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT, vlan_accept_untagged_packets); } void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_untagged_act_adr, - rpf_vl_untagged_act_msk, - rpf_vl_untagged_act_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR, + HW_ATL_RPF_VL_UNTAGGED_ACT_MSK, + HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT, vlan_untagged_act); } void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_en_f_adr(filter), - rpf_vl_en_f_msk, - rpf_vl_en_f_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter), + HW_ATL_RPF_VL_EN_F_MSK, + HW_ATL_RPF_VL_EN_F_SHIFT, vlan_flr_en); } void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_act_f_adr(filter), - rpf_vl_act_f_msk, - rpf_vl_act_f_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter), + HW_ATL_RPF_VL_ACT_F_MSK, + HW_ATL_RPF_VL_ACT_F_SHIFT, vlan_flr_act); } void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_vl_id_f_adr(filter), - rpf_vl_id_f_msk, - rpf_vl_id_f_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter), + HW_ATL_RPF_VL_ID_F_MSK, + HW_ATL_RPF_VL_ID_F_SHIFT, vlan_id_flr); } void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_enf_adr(filter), - rpf_et_enf_msk, - rpf_et_enf_shift, etht_flr_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter), + HW_ATL_RPF_ET_ENF_MSK, + HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en); } void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, u32 etht_user_priority_en, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_upfen_adr(filter), - rpf_et_upfen_msk, rpf_et_upfen_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter), + HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT, etht_user_priority_en); } void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_rxqfen_adr(filter), - rpf_et_rxqfen_msk, rpf_et_rxqfen_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter), + HW_ATL_RPF_ET_RXQFEN_MSK, + HW_ATL_RPF_ET_RXQFEN_SHIFT, etht_rx_queue_en); } void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_upf_adr(filter), - rpf_et_upf_msk, - rpf_et_upf_shift, etht_user_priority); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter), + HW_ATL_RPF_ET_UPF_MSK, + HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority); } void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_rxqf_adr(filter), - rpf_et_rxqf_msk, - rpf_et_rxqf_shift, etht_rx_queue); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter), + HW_ATL_RPF_ET_RXQF_MSK, + HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue); } void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_mng_rxqf_adr(filter), - rpf_et_mng_rxqf_msk, rpf_et_mng_rxqf_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter), + HW_ATL_RPF_ET_MNG_RXQF_MSK, + HW_ATL_RPF_ET_MNG_RXQF_SHIFT, etht_mgt_queue); } void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_actf_adr(filter), - rpf_et_actf_msk, - rpf_et_actf_shift, etht_flr_act); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter), + HW_ATL_RPF_ET_ACTF_MSK, + HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act); } void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter) { - aq_hw_write_reg_bit(aq_hw, rpf_et_valf_adr(filter), - rpf_et_valf_msk, - rpf_et_valf_shift, etht_flr); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter), + HW_ATL_RPF_ET_VALF_MSK, + HW_ATL_RPF_ET_VALF_SHIFT, etht_flr); } /* RPO: rx packet offload */ void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, u32 ipv4header_crc_offload_en) { - aq_hw_write_reg_bit(aq_hw, rpo_ipv4chk_en_adr, - rpo_ipv4chk_en_msk, - rpo_ipv4chk_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR, + HW_ATL_RPO_IPV4CHK_EN_MSK, + HW_ATL_RPO_IPV4CHK_EN_SHIFT, ipv4header_crc_offload_en); } void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, u32 rx_desc_vlan_stripping, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, rpo_descdvl_strip_adr(descriptor), - rpo_descdvl_strip_msk, - rpo_descdvl_strip_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor), + HW_ATL_RPO_DESCDVL_STRIP_MSK, + HW_ATL_RPO_DESCDVL_STRIP_SHIFT, rx_desc_vlan_stripping); } void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, u32 tcp_udp_crc_offload_en) { - aq_hw_write_reg_bit(aq_hw, rpol4chk_en_adr, rpol4chk_en_msk, - rpol4chk_en_shift, tcp_udp_crc_offload_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR, + HW_ATL_RPOL4CHK_EN_MSK, + HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en); } void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en) { - aq_hw_write_reg(aq_hw, rpo_lro_en_adr, lro_en); + aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en); } void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, u32 lro_patch_optimization_en) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_ptopt_en_adr, - rpo_lro_ptopt_en_msk, - rpo_lro_ptopt_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR, + HW_ATL_RPO_LRO_PTOPT_EN_MSK, + HW_ATL_RPO_LRO_PTOPT_EN_SHIFT, lro_patch_optimization_en); } void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, u32 lro_qsessions_lim) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_qses_lmt_adr, - rpo_lro_qses_lmt_msk, - rpo_lro_qses_lmt_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR, + HW_ATL_RPO_LRO_QSES_LMT_MSK, + HW_ATL_RPO_LRO_QSES_LMT_SHIFT, lro_qsessions_lim); } void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_tot_dsc_lmt_adr, - rpo_lro_tot_dsc_lmt_msk, - rpo_lro_tot_dsc_lmt_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR, + HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK, + HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT, lro_total_desc_lim); } void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, u32 lro_min_pld_of_first_pkt) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_pkt_min_adr, - rpo_lro_pkt_min_msk, - rpo_lro_pkt_min_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR, + HW_ATL_RPO_LRO_PKT_MIN_MSK, + HW_ATL_RPO_LRO_PKT_MIN_SHIFT, lro_min_pld_of_first_pkt); } void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim) { - aq_hw_write_reg(aq_hw, rpo_lro_rsc_max_adr, lro_pkt_lim); + aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim); } void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, @@ -1020,101 +1038,104 @@ void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, u32 lro_time_base_divider) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_tb_div_adr, - rpo_lro_tb_div_msk, - rpo_lro_tb_div_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR, + HW_ATL_RPO_LRO_TB_DIV_MSK, + HW_ATL_RPO_LRO_TB_DIV_SHIFT, lro_time_base_divider); } void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, u32 lro_inactive_interval) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_ina_ival_adr, - rpo_lro_ina_ival_msk, - rpo_lro_ina_ival_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR, + HW_ATL_RPO_LRO_INA_IVAL_MSK, + HW_ATL_RPO_LRO_INA_IVAL_SHIFT, lro_inactive_interval); } void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, u32 lro_max_coalescing_interval) { - aq_hw_write_reg_bit(aq_hw, rpo_lro_max_ival_adr, - rpo_lro_max_ival_msk, - rpo_lro_max_ival_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR, + HW_ATL_RPO_LRO_MAX_IVAL_MSK, + HW_ATL_RPO_LRO_MAX_IVAL_SHIFT, lro_max_coalescing_interval); } /* rx */ void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis) { - aq_hw_write_reg_bit(aq_hw, rx_reg_res_dsbl_adr, - rx_reg_res_dsbl_msk, - rx_reg_res_dsbl_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR, + HW_ATL_RX_REG_RES_DSBL_MSK, + HW_ATL_RX_REG_RES_DSBL_SHIFT, rx_reg_res_dis); } /* tdm */ void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) { - aq_hw_write_reg_bit(aq_hw, tdm_dcadcpuid_adr(dca), - tdm_dcadcpuid_msk, - tdm_dcadcpuid_shift, cpuid); + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca), + HW_ATL_TDM_DCADCPUID_MSK, + HW_ATL_TDM_DCADCPUID_SHIFT, cpuid); } void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, u32 large_send_offload_en) { - aq_hw_write_reg(aq_hw, tdm_lso_en_adr, large_send_offload_en); + aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en); } void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en) { - aq_hw_write_reg_bit(aq_hw, tdm_dca_en_adr, tdm_dca_en_msk, - tdm_dca_en_shift, tx_dca_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK, + HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en); } void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode) { - aq_hw_write_reg_bit(aq_hw, tdm_dca_mode_adr, tdm_dca_mode_msk, - tdm_dca_mode_shift, tx_dca_mode); + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR, + HW_ATL_TDM_DCA_MODE_MSK, + HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode); } void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca) { - aq_hw_write_reg_bit(aq_hw, tdm_dcaddesc_en_adr(dca), - tdm_dcaddesc_en_msk, tdm_dcaddesc_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca), + HW_ATL_TDM_DCADDESC_EN_MSK, + HW_ATL_TDM_DCADDESC_EN_SHIFT, tx_desc_dca_en); } void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, tdm_descden_adr(descriptor), - tdm_descden_msk, - tdm_descden_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor), + HW_ATL_TDM_DESCDEN_MSK, + HW_ATL_TDM_DESCDEN_SHIFT, tx_desc_en); } u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) { - return aq_hw_read_reg_bit(aq_hw, tdm_descdhd_adr(descriptor), - tdm_descdhd_msk, tdm_descdhd_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor), + HW_ATL_TDM_DESCDHD_MSK, + HW_ATL_TDM_DESCDHD_SHIFT); } void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, tdm_descdlen_adr(descriptor), - tdm_descdlen_msk, - tdm_descdlen_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor), + HW_ATL_TDM_DESCDLEN_MSK, + HW_ATL_TDM_DESCDLEN_SHIFT, tx_desc_len); } void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_wr_wb_irq_en) { - aq_hw_write_reg_bit(aq_hw, tdm_int_desc_wrb_en_adr, - tdm_int_desc_wrb_en_msk, - tdm_int_desc_wrb_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR, + HW_ATL_TDM_INT_DESC_WRB_EN_MSK, + HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT, tx_desc_wr_wb_irq_en); } @@ -1122,18 +1143,18 @@ void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, u32 tx_desc_wr_wb_threshold, u32 descriptor) { - aq_hw_write_reg_bit(aq_hw, tdm_descdwrb_thresh_adr(descriptor), - tdm_descdwrb_thresh_msk, - tdm_descdwrb_thresh_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor), + HW_ATL_TDM_DESCDWRB_THRESH_MSK, + HW_ATL_TDM_DESCDWRB_THRESH_SHIFT, tx_desc_wr_wb_threshold); } void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 tdm_irq_moderation_en) { - aq_hw_write_reg_bit(aq_hw, tdm_int_mod_en_adr, - tdm_int_mod_en_msk, - tdm_int_mod_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR, + HW_ATL_TDM_INT_MOD_EN_MSK, + HW_ATL_TDM_INT_MOD_EN_SHIFT, tdm_irq_moderation_en); } @@ -1141,43 +1162,45 @@ void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, u32 lso_tcp_flag_of_first_pkt) { - aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_first_adr, - thm_lso_tcp_flag_first_msk, - thm_lso_tcp_flag_first_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR, + HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK, + HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT, lso_tcp_flag_of_first_pkt); } void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, u32 lso_tcp_flag_of_last_pkt) { - aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_last_adr, - thm_lso_tcp_flag_last_msk, - thm_lso_tcp_flag_last_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR, + HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK, + HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT, lso_tcp_flag_of_last_pkt); } void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, u32 lso_tcp_flag_of_middle_pkt) { - aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_mid_adr, - thm_lso_tcp_flag_mid_msk, - thm_lso_tcp_flag_mid_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR, + HW_ATL_THM_LSO_TCP_FLAG_MID_MSK, + HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT, lso_tcp_flag_of_middle_pkt); } /* TPB: tx packet buffer */ void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en) { - aq_hw_write_reg_bit(aq_hw, tpb_tx_buf_en_adr, tpb_tx_buf_en_msk, - tpb_tx_buf_en_shift, tx_buff_en); + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR, + HW_ATL_TPB_TX_BUF_EN_MSK, + HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en); } void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, u32 tx_buff_hi_threshold_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, tpb_txbhi_thresh_adr(buffer), - tpb_txbhi_thresh_msk, tpb_txbhi_thresh_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer), + HW_ATL_TPB_TXBHI_THRESH_MSK, + HW_ATL_TPB_TXBHI_THRESH_SHIFT, tx_buff_hi_threshold_per_tc); } @@ -1185,33 +1208,34 @@ void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, u32 tx_buff_lo_threshold_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, tpb_txblo_thresh_adr(buffer), - tpb_txblo_thresh_msk, tpb_txblo_thresh_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer), + HW_ATL_TPB_TXBLO_THRESH_MSK, + HW_ATL_TPB_TXBLO_THRESH_SHIFT, tx_buff_lo_threshold_per_tc); } void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en) { - aq_hw_write_reg_bit(aq_hw, tpb_dma_sys_lbk_adr, - tpb_dma_sys_lbk_msk, - tpb_dma_sys_lbk_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR, + HW_ATL_TPB_DMA_SYS_LBK_MSK, + HW_ATL_TPB_DMA_SYS_LBK_SHIFT, tx_dma_sys_lbk_en); } void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, u32 tx_pkt_buff_size_per_tc, u32 buffer) { - aq_hw_write_reg_bit(aq_hw, tpb_txbbuf_size_adr(buffer), - tpb_txbbuf_size_msk, - tpb_txbbuf_size_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer), + HW_ATL_TPB_TXBBUF_SIZE_MSK, + HW_ATL_TPB_TXBBUF_SIZE_SHIFT, tx_pkt_buff_size_per_tc); } void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en) { - aq_hw_write_reg_bit(aq_hw, tpb_tx_scp_ins_en_adr, - tpb_tx_scp_ins_en_msk, - tpb_tx_scp_ins_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR, + HW_ATL_TPB_TX_SCP_INS_EN_MSK, + HW_ATL_TPB_TX_SCP_INS_EN_SHIFT, tx_path_scp_ins_en); } @@ -1219,26 +1243,26 @@ void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en) void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, u32 ipv4header_crc_offload_en) { - aq_hw_write_reg_bit(aq_hw, tpo_ipv4chk_en_adr, - tpo_ipv4chk_en_msk, - tpo_ipv4chk_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR, + HW_ATL_TPO_IPV4CHK_EN_MSK, + HW_ATL_TPO_IPV4CHK_EN_SHIFT, ipv4header_crc_offload_en); } void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, u32 tcp_udp_crc_offload_en) { - aq_hw_write_reg_bit(aq_hw, tpol4chk_en_adr, - tpol4chk_en_msk, - tpol4chk_en_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR, + HW_ATL_TPOL4CHK_EN_MSK, + HW_ATL_TPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en); } void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en) { - aq_hw_write_reg_bit(aq_hw, tpo_pkt_sys_lbk_adr, - tpo_pkt_sys_lbk_msk, - tpo_pkt_sys_lbk_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR, + HW_ATL_TPO_PKT_SYS_LBK_MSK, + HW_ATL_TPO_PKT_SYS_LBK_SHIFT, tx_pkt_sys_lbk_en); } @@ -1246,36 +1270,36 @@ void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en) void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_data_arb_mode) { - aq_hw_write_reg_bit(aq_hw, tps_data_tc_arb_mode_adr, - tps_data_tc_arb_mode_msk, - tps_data_tc_arb_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR, + HW_ATL_TPS_DATA_TC_ARB_MODE_MSK, + HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT, tx_pkt_shed_data_arb_mode); } void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, u32 curr_time_res) { - aq_hw_write_reg_bit(aq_hw, tps_desc_rate_ta_rst_adr, - tps_desc_rate_ta_rst_msk, - tps_desc_rate_ta_rst_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR, + HW_ATL_TPS_DESC_RATE_TA_RST_MSK, + HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT, curr_time_res); } void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_desc_rate_lim) { - aq_hw_write_reg_bit(aq_hw, tps_desc_rate_lim_adr, - tps_desc_rate_lim_msk, - tps_desc_rate_lim_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR, + HW_ATL_TPS_DESC_RATE_LIM_MSK, + HW_ATL_TPS_DESC_RATE_LIM_SHIFT, tx_pkt_shed_desc_rate_lim); } void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_desc_tc_arb_mode) { - aq_hw_write_reg_bit(aq_hw, tps_desc_tc_arb_mode_adr, - tps_desc_tc_arb_mode_msk, - tps_desc_tc_arb_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR, + HW_ATL_TPS_DESC_TC_ARB_MODE_MSK, + HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT, tx_pkt_shed_desc_tc_arb_mode); } @@ -1283,27 +1307,27 @@ void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_desc_tc_max_credit, u32 tc) { - aq_hw_write_reg_bit(aq_hw, tps_desc_tctcredit_max_adr(tc), - tps_desc_tctcredit_max_msk, - tps_desc_tctcredit_max_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc), + HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK, + HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT, tx_pkt_shed_desc_tc_max_credit); } void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_desc_tc_weight, u32 tc) { - aq_hw_write_reg_bit(aq_hw, tps_desc_tctweight_adr(tc), - tps_desc_tctweight_msk, - tps_desc_tctweight_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc), + HW_ATL_TPS_DESC_TCTWEIGHT_MSK, + HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT, tx_pkt_shed_desc_tc_weight); } void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_desc_vm_arb_mode) { - aq_hw_write_reg_bit(aq_hw, tps_desc_vm_arb_mode_adr, - tps_desc_vm_arb_mode_msk, - tps_desc_vm_arb_mode_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR, + HW_ATL_TPS_DESC_VM_ARB_MODE_MSK, + HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT, tx_pkt_shed_desc_vm_arb_mode); } @@ -1311,84 +1335,84 @@ void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_tc_data_max_credit, u32 tc) { - aq_hw_write_reg_bit(aq_hw, tps_data_tctcredit_max_adr(tc), - tps_data_tctcredit_max_msk, - tps_data_tctcredit_max_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc), + HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK, + HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT, tx_pkt_shed_tc_data_max_credit); } void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, u32 tx_pkt_shed_tc_data_weight, u32 tc) { - aq_hw_write_reg_bit(aq_hw, tps_data_tctweight_adr(tc), - tps_data_tctweight_msk, - tps_data_tctweight_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc), + HW_ATL_TPS_DATA_TCTWEIGHT_MSK, + HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT, tx_pkt_shed_tc_data_weight); } /* tx */ void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis) { - aq_hw_write_reg_bit(aq_hw, tx_reg_res_dsbl_adr, - tx_reg_res_dsbl_msk, - tx_reg_res_dsbl_shift, tx_reg_res_dis); + aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR, + HW_ATL_TX_REG_RES_DSBL_MSK, + HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis); } /* msm */ u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg_bit(aq_hw, msm_reg_access_busy_adr, - msm_reg_access_busy_msk, - msm_reg_access_busy_shift); + return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR, + HW_ATL_MSM_REG_ACCESS_BUSY_MSK, + HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT); } void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, u32 reg_addr_for_indirect_addr) { - aq_hw_write_reg_bit(aq_hw, msm_reg_addr_adr, - msm_reg_addr_msk, - msm_reg_addr_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR, + HW_ATL_MSM_REG_ADDR_MSK, + HW_ATL_MSM_REG_ADDR_SHIFT, reg_addr_for_indirect_addr); } void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe) { - aq_hw_write_reg_bit(aq_hw, msm_reg_rd_strobe_adr, - msm_reg_rd_strobe_msk, - msm_reg_rd_strobe_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR, + HW_ATL_MSM_REG_RD_STROBE_MSK, + HW_ATL_MSM_REG_RD_STROBE_SHIFT, reg_rd_strobe); } u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw) { - return aq_hw_read_reg(aq_hw, msm_reg_rd_data_adr); + return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR); } void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data) { - aq_hw_write_reg(aq_hw, msm_reg_wr_data_adr, reg_wr_data); + aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data); } void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe) { - aq_hw_write_reg_bit(aq_hw, msm_reg_wr_strobe_adr, - msm_reg_wr_strobe_msk, - msm_reg_wr_strobe_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR, + HW_ATL_MSM_REG_WR_STROBE_MSK, + HW_ATL_MSM_REG_WR_STROBE_SHIFT, reg_wr_strobe); } /* pci */ void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis) { - aq_hw_write_reg_bit(aq_hw, pci_reg_res_dsbl_adr, - pci_reg_res_dsbl_msk, - pci_reg_res_dsbl_shift, + aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR, + HW_ATL_PCI_REG_RES_DSBL_MSK, + HW_ATL_PCI_REG_RES_DSBL_SHIFT, pci_reg_res_dis); } void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, u32 glb_cpu_scratch_scp, u32 scratch_scp) { - aq_hw_write_reg(aq_hw, glb_cpu_scratch_scp_adr(scratch_scp), + aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp), glb_cpu_scratch_scp); } diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h index 93450ec930e8..e0cf70120f1d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h @@ -18,91 +18,91 @@ * base address: 0x000003a0 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] */ -#define glb_cpu_sem_adr(semaphore) (0x000003a0u + (semaphore) * 0x4) +#define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) /* register address for bitfield rx dma good octet counter lsw [1f:0] */ -#define stats_rx_dma_good_octet_counterlsw__adr 0x00006808 +#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ -#define stats_rx_dma_good_pkt_counterlsw__adr 0x00006800 +#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ -#define stats_tx_dma_good_octet_counterlsw__adr 0x00008808 +#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ -#define stats_tx_dma_good_pkt_counterlsw__adr 0x00008800 +#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 /* register address for bitfield rx dma good octet counter msw [3f:20] */ -#define stats_rx_dma_good_octet_countermsw__adr 0x0000680c +#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c /* register address for bitfield rx dma good packet counter msw [3f:20] */ -#define stats_rx_dma_good_pkt_countermsw__adr 0x00006804 +#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 /* register address for bitfield tx dma good octet counter msw [3f:20] */ -#define stats_tx_dma_good_octet_countermsw__adr 0x0000880c +#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c /* register address for bitfield tx dma good packet counter msw [3f:20] */ -#define stats_tx_dma_good_pkt_countermsw__adr 0x00008804 +#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 /* preprocessor definitions for msm rx errors counter register */ -#define mac_msm_rx_errs_cnt_adr 0x00000120u +#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u /* preprocessor definitions for msm rx unicast frames counter register */ -#define mac_msm_rx_ucst_frm_cnt_adr 0x000000e0u +#define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u /* preprocessor definitions for msm rx multicast frames counter register */ -#define mac_msm_rx_mcst_frm_cnt_adr 0x000000e8u +#define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u /* preprocessor definitions for msm rx broadcast frames counter register */ -#define mac_msm_rx_bcst_frm_cnt_adr 0x000000f0u +#define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u /* preprocessor definitions for msm rx broadcast octets counter register 1 */ -#define mac_msm_rx_bcst_octets_counter1_adr 0x000001b0u +#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u /* preprocessor definitions for msm rx broadcast octets counter register 2 */ -#define mac_msm_rx_bcst_octets_counter2_adr 0x000001b4u +#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u /* preprocessor definitions for msm rx unicast octets counter register 0 */ -#define mac_msm_rx_ucst_octets_counter0_adr 0x000001b8u +#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u /* preprocessor definitions for rx dma statistics counter 7 */ -#define rx_dma_stat_counter7_adr 0x00006818u +#define HW_ATL_RX_DMA_STAT_COUNTER7_ADR 0x00006818u /* preprocessor definitions for msm tx unicast frames counter register */ -#define mac_msm_tx_ucst_frm_cnt_adr 0x00000108u +#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u /* preprocessor definitions for msm tx multicast frames counter register */ -#define mac_msm_tx_mcst_frm_cnt_adr 0x00000110u +#define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u /* preprocessor definitions for global mif identification */ -#define glb_mif_id_adr 0x0000001cu +#define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu /* register address for bitfield iamr_lsw[1f:0] */ -#define itr_iamrlsw_adr 0x00002090 +#define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 /* register address for bitfield rx dma drop packet counter [1f:0] */ -#define rpb_rx_dma_drop_pkt_cnt_adr 0x00006818 +#define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 /* register address for bitfield imcr_lsw[1f:0] */ -#define itr_imcrlsw_adr 0x00002070 +#define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 /* register address for bitfield imsr_lsw[1f:0] */ -#define itr_imsrlsw_adr 0x00002060 +#define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 /* register address for bitfield itr_reg_res_dsbl */ -#define itr_reg_res_dsbl_adr 0x00002300 +#define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 /* bitmask for bitfield itr_reg_res_dsbl */ -#define itr_reg_res_dsbl_msk 0x20000000 +#define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 /* lower bit position of bitfield itr_reg_res_dsbl */ -#define itr_reg_res_dsbl_shift 29 +#define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 /* register address for bitfield iscr_lsw[1f:0] */ -#define itr_iscrlsw_adr 0x00002050 +#define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 /* register address for bitfield isr_lsw[1f:0] */ -#define itr_isrlsw_adr 0x00002000 +#define HW_ATL_ITR_ISRLSW_ADR 0x00002000 /* register address for bitfield itr_reset */ -#define itr_res_adr 0x00002300 +#define HW_ATL_ITR_RES_ADR 0x00002300 /* bitmask for bitfield itr_reset */ -#define itr_res_msk 0x80000000 +#define HW_ATL_ITR_RES_MSK 0x80000000 /* lower bit position of bitfield itr_reset */ -#define itr_res_shift 31 +#define HW_ATL_ITR_RES_SHIFT 31 /* register address for bitfield dca{d}_cpuid[7:0] */ -#define rdm_dcadcpuid_adr(dca) (0x00006100 + (dca) * 0x4) +#define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) /* bitmask for bitfield dca{d}_cpuid[7:0] */ -#define rdm_dcadcpuid_msk 0x000000ff +#define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff /* lower bit position of bitfield dca{d}_cpuid[7:0] */ -#define rdm_dcadcpuid_shift 0 +#define HW_ATL_RDM_DCADCPUID_SHIFT 0 /* register address for bitfield dca_en */ -#define rdm_dca_en_adr 0x00006180 +#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 /* rx dca_en bitfield definitions * preprocessor definitions for the bitfield "dca_en". @@ -110,17 +110,17 @@ */ /* register address for bitfield dca_en */ -#define rdm_dca_en_adr 0x00006180 +#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 /* bitmask for bitfield dca_en */ -#define rdm_dca_en_msk 0x80000000 +#define HW_ATL_RDM_DCA_EN_MSK 0x80000000 /* inverted bitmask for bitfield dca_en */ -#define rdm_dca_en_mskn 0x7fffffff +#define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff /* lower bit position of bitfield dca_en */ -#define rdm_dca_en_shift 31 +#define HW_ATL_RDM_DCA_EN_SHIFT 31 /* width of bitfield dca_en */ -#define rdm_dca_en_width 1 +#define HW_ATL_RDM_DCA_EN_WIDTH 1 /* default value of bitfield dca_en */ -#define rdm_dca_en_default 0x1 +#define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 /* rx dca_mode[3:0] bitfield definitions * preprocessor definitions for the bitfield "dca_mode[3:0]". @@ -128,17 +128,17 @@ */ /* register address for bitfield dca_mode[3:0] */ -#define rdm_dca_mode_adr 0x00006180 +#define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 /* bitmask for bitfield dca_mode[3:0] */ -#define rdm_dca_mode_msk 0x0000000f +#define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f /* inverted bitmask for bitfield dca_mode[3:0] */ -#define rdm_dca_mode_mskn 0xfffffff0 +#define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 /* lower bit position of bitfield dca_mode[3:0] */ -#define rdm_dca_mode_shift 0 +#define HW_ATL_RDM_DCA_MODE_SHIFT 0 /* width of bitfield dca_mode[3:0] */ -#define rdm_dca_mode_width 4 +#define HW_ATL_RDM_DCA_MODE_WIDTH 4 /* default value of bitfield dca_mode[3:0] */ -#define rdm_dca_mode_default 0x0 +#define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 /* rx desc{d}_data_size[4:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". @@ -147,17 +147,18 @@ */ /* register address for bitfield desc{d}_data_size[4:0] */ -#define rdm_descddata_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ + (0x00005b18 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_data_size[4:0] */ -#define rdm_descddata_size_msk 0x0000001f +#define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ -#define rdm_descddata_size_mskn 0xffffffe0 +#define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 /* lower bit position of bitfield desc{d}_data_size[4:0] */ -#define rdm_descddata_size_shift 0 +#define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 /* width of bitfield desc{d}_data_size[4:0] */ -#define rdm_descddata_size_width 5 +#define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 /* default value of bitfield desc{d}_data_size[4:0] */ -#define rdm_descddata_size_default 0x0 +#define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 /* rx dca{d}_desc_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_desc_en". @@ -166,17 +167,17 @@ */ /* register address for bitfield dca{d}_desc_en */ -#define rdm_dcaddesc_en_adr(dca) (0x00006100 + (dca) * 0x4) +#define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) /* bitmask for bitfield dca{d}_desc_en */ -#define rdm_dcaddesc_en_msk 0x80000000 +#define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 /* inverted bitmask for bitfield dca{d}_desc_en */ -#define rdm_dcaddesc_en_mskn 0x7fffffff +#define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff /* lower bit position of bitfield dca{d}_desc_en */ -#define rdm_dcaddesc_en_shift 31 +#define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 /* width of bitfield dca{d}_desc_en */ -#define rdm_dcaddesc_en_width 1 +#define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 /* default value of bitfield dca{d}_desc_en */ -#define rdm_dcaddesc_en_default 0x0 +#define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 /* rx desc{d}_en bitfield definitions * preprocessor definitions for the bitfield "desc{d}_en". @@ -185,17 +186,17 @@ */ /* register address for bitfield desc{d}_en */ -#define rdm_descden_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_en */ -#define rdm_descden_msk 0x80000000 +#define HW_ATL_RDM_DESCDEN_MSK 0x80000000 /* inverted bitmask for bitfield desc{d}_en */ -#define rdm_descden_mskn 0x7fffffff +#define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff /* lower bit position of bitfield desc{d}_en */ -#define rdm_descden_shift 31 +#define HW_ATL_RDM_DESCDEN_SHIFT 31 /* width of bitfield desc{d}_en */ -#define rdm_descden_width 1 +#define HW_ATL_RDM_DESCDEN_WIDTH 1 /* default value of bitfield desc{d}_en */ -#define rdm_descden_default 0x0 +#define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 /* rx desc{d}_hdr_size[4:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". @@ -204,17 +205,18 @@ */ /* register address for bitfield desc{d}_hdr_size[4:0] */ -#define rdm_descdhdr_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ + (0x00005b18 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_hdr_size[4:0] */ -#define rdm_descdhdr_size_msk 0x00001f00 +#define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ -#define rdm_descdhdr_size_mskn 0xffffe0ff +#define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ -#define rdm_descdhdr_size_shift 8 +#define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 /* width of bitfield desc{d}_hdr_size[4:0] */ -#define rdm_descdhdr_size_width 5 +#define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 /* default value of bitfield desc{d}_hdr_size[4:0] */ -#define rdm_descdhdr_size_default 0x0 +#define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 /* rx desc{d}_hdr_split bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hdr_split". @@ -223,17 +225,18 @@ */ /* register address for bitfield desc{d}_hdr_split */ -#define rdm_descdhdr_split_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ + (0x00005b08 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_hdr_split */ -#define rdm_descdhdr_split_msk 0x10000000 +#define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 /* inverted bitmask for bitfield desc{d}_hdr_split */ -#define rdm_descdhdr_split_mskn 0xefffffff +#define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff /* lower bit position of bitfield desc{d}_hdr_split */ -#define rdm_descdhdr_split_shift 28 +#define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 /* width of bitfield desc{d}_hdr_split */ -#define rdm_descdhdr_split_width 1 +#define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 /* default value of bitfield desc{d}_hdr_split */ -#define rdm_descdhdr_split_default 0x0 +#define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 /* rx desc{d}_hd[c:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". @@ -242,15 +245,15 @@ */ /* register address for bitfield desc{d}_hd[c:0] */ -#define rdm_descdhd_adr(descriptor) (0x00005b0c + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_hd[c:0] */ -#define rdm_descdhd_msk 0x00001fff +#define HW_ATL_RDM_DESCDHD_MSK 0x00001fff /* inverted bitmask for bitfield desc{d}_hd[c:0] */ -#define rdm_descdhd_mskn 0xffffe000 +#define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 /* lower bit position of bitfield desc{d}_hd[c:0] */ -#define rdm_descdhd_shift 0 +#define HW_ATL_RDM_DESCDHD_SHIFT 0 /* width of bitfield desc{d}_hd[c:0] */ -#define rdm_descdhd_width 13 +#define HW_ATL_RDM_DESCDHD_WIDTH 13 /* rx desc{d}_len[9:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_len[9:0]". @@ -259,17 +262,17 @@ */ /* register address for bitfield desc{d}_len[9:0] */ -#define rdm_descdlen_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_len[9:0] */ -#define rdm_descdlen_msk 0x00001ff8 +#define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 /* inverted bitmask for bitfield desc{d}_len[9:0] */ -#define rdm_descdlen_mskn 0xffffe007 +#define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 /* lower bit position of bitfield desc{d}_len[9:0] */ -#define rdm_descdlen_shift 3 +#define HW_ATL_RDM_DESCDLEN_SHIFT 3 /* width of bitfield desc{d}_len[9:0] */ -#define rdm_descdlen_width 10 +#define HW_ATL_RDM_DESCDLEN_WIDTH 10 /* default value of bitfield desc{d}_len[9:0] */ -#define rdm_descdlen_default 0x0 +#define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 /* rx desc{d}_reset bitfield definitions * preprocessor definitions for the bitfield "desc{d}_reset". @@ -278,17 +281,17 @@ */ /* register address for bitfield desc{d}_reset */ -#define rdm_descdreset_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) +#define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_reset */ -#define rdm_descdreset_msk 0x02000000 +#define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 /* inverted bitmask for bitfield desc{d}_reset */ -#define rdm_descdreset_mskn 0xfdffffff +#define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff /* lower bit position of bitfield desc{d}_reset */ -#define rdm_descdreset_shift 25 +#define HW_ATL_RDM_DESCDRESET_SHIFT 25 /* width of bitfield desc{d}_reset */ -#define rdm_descdreset_width 1 +#define HW_ATL_RDM_DESCDRESET_WIDTH 1 /* default value of bitfield desc{d}_reset */ -#define rdm_descdreset_default 0x0 +#define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 /* rx int_desc_wrb_en bitfield definitions * preprocessor definitions for the bitfield "int_desc_wrb_en". @@ -296,17 +299,17 @@ */ /* register address for bitfield int_desc_wrb_en */ -#define rdm_int_desc_wrb_en_adr 0x00005a30 +#define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 /* bitmask for bitfield int_desc_wrb_en */ -#define rdm_int_desc_wrb_en_msk 0x00000004 +#define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 /* inverted bitmask for bitfield int_desc_wrb_en */ -#define rdm_int_desc_wrb_en_mskn 0xfffffffb +#define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb /* lower bit position of bitfield int_desc_wrb_en */ -#define rdm_int_desc_wrb_en_shift 2 +#define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 /* width of bitfield int_desc_wrb_en */ -#define rdm_int_desc_wrb_en_width 1 +#define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 /* default value of bitfield int_desc_wrb_en */ -#define rdm_int_desc_wrb_en_default 0x0 +#define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 /* rx dca{d}_hdr_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_hdr_en". @@ -315,17 +318,17 @@ */ /* register address for bitfield dca{d}_hdr_en */ -#define rdm_dcadhdr_en_adr(dca) (0x00006100 + (dca) * 0x4) +#define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) /* bitmask for bitfield dca{d}_hdr_en */ -#define rdm_dcadhdr_en_msk 0x40000000 +#define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 /* inverted bitmask for bitfield dca{d}_hdr_en */ -#define rdm_dcadhdr_en_mskn 0xbfffffff +#define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff /* lower bit position of bitfield dca{d}_hdr_en */ -#define rdm_dcadhdr_en_shift 30 +#define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 /* width of bitfield dca{d}_hdr_en */ -#define rdm_dcadhdr_en_width 1 +#define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 /* default value of bitfield dca{d}_hdr_en */ -#define rdm_dcadhdr_en_default 0x0 +#define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 /* rx dca{d}_pay_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_pay_en". @@ -334,17 +337,17 @@ */ /* register address for bitfield dca{d}_pay_en */ -#define rdm_dcadpay_en_adr(dca) (0x00006100 + (dca) * 0x4) +#define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) /* bitmask for bitfield dca{d}_pay_en */ -#define rdm_dcadpay_en_msk 0x20000000 +#define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 /* inverted bitmask for bitfield dca{d}_pay_en */ -#define rdm_dcadpay_en_mskn 0xdfffffff +#define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff /* lower bit position of bitfield dca{d}_pay_en */ -#define rdm_dcadpay_en_shift 29 +#define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 /* width of bitfield dca{d}_pay_en */ -#define rdm_dcadpay_en_width 1 +#define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 /* default value of bitfield dca{d}_pay_en */ -#define rdm_dcadpay_en_default 0x0 +#define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 /* RX rdm_int_rim_en Bitfield Definitions * Preprocessor definitions for the bitfield "rdm_int_rim_en". @@ -352,51 +355,51 @@ */ /* Register address for bitfield rdm_int_rim_en */ -#define rdm_int_rim_en_adr 0x00005A30 +#define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 /* Bitmask for bitfield rdm_int_rim_en */ -#define rdm_int_rim_en_msk 0x00000008 +#define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 /* Inverted bitmask for bitfield rdm_int_rim_en */ -#define rdm_int_rim_en_mskn 0xFFFFFFF7 +#define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 /* Lower bit position of bitfield rdm_int_rim_en */ -#define rdm_int_rim_en_shift 3 +#define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 /* Width of bitfield rdm_int_rim_en */ -#define rdm_int_rim_en_width 1 +#define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 /* Default value of bitfield rdm_int_rim_en */ -#define rdm_int_rim_en_default 0x0 +#define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 /* general interrupt mapping register definitions * preprocessor definitions for general interrupt mapping register * base address: 0x00002180 * parameter: regidx {f} | stride size 0x4 | range [0, 3] */ -#define gen_intr_map_adr(regidx) (0x00002180u + (regidx) * 0x4) +#define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) /* general interrupt status register definitions * preprocessor definitions for general interrupt status register * address: 0x000021A0 */ -#define gen_intr_stat_adr 0x000021A4U +#define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U /* interrupt global control register definitions * preprocessor definitions for interrupt global control register * address: 0x00002300 */ -#define intr_glb_ctl_adr 0x00002300u +#define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u /* interrupt throttle register definitions * preprocessor definitions for interrupt throttle register * base address: 0x00002800 * parameter: throttle {t} | stride size 0x4 | range [0, 31] */ -#define intr_thr_adr(throttle) (0x00002800u + (throttle) * 0x4) +#define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) /* rx dma descriptor base address lsw definitions * preprocessor definitions for rx dma descriptor base address lsw * base address: 0x00005b00 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ -#define rx_dma_desc_base_addrlsw_adr(descriptor) \ +#define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ (0x00005b00u + (descriptor) * 0x20) /* rx dma descriptor base address msw definitions @@ -404,7 +407,7 @@ * base address: 0x00005b04 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ -#define rx_dma_desc_base_addrmsw_adr(descriptor) \ +#define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ (0x00005b04u + (descriptor) * 0x20) /* rx dma descriptor status register definitions @@ -412,46 +415,48 @@ * base address: 0x00005b14 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ -#define rx_dma_desc_stat_adr(descriptor) (0x00005b14u + (descriptor) * 0x20) +#define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ + (0x00005b14u + (descriptor) * 0x20) /* rx dma descriptor tail pointer register definitions * preprocessor definitions for rx dma descriptor tail pointer register * base address: 0x00005b10 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ -#define rx_dma_desc_tail_ptr_adr(descriptor) (0x00005b10u + (descriptor) * 0x20) +#define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ + (0x00005b10u + (descriptor) * 0x20) /* rx interrupt moderation control register definitions * Preprocessor definitions for RX Interrupt Moderation Control Register * Base Address: 0x00005A40 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] */ -#define rx_intr_moderation_ctl_adr(rim) (0x00005A40u + (rim) * 0x4) +#define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) /* rx filter multicast filter mask register definitions * preprocessor definitions for rx filter multicast filter mask register * address: 0x00005270 */ -#define rx_flr_mcst_flr_msk_adr 0x00005270u +#define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u /* rx filter multicast filter register definitions * preprocessor definitions for rx filter multicast filter register * base address: 0x00005250 * parameter: filter {f} | stride size 0x4 | range [0, 7] */ -#define rx_flr_mcst_flr_adr(filter) (0x00005250u + (filter) * 0x4) +#define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) /* RX Filter RSS Control Register 1 Definitions * Preprocessor definitions for RX Filter RSS Control Register 1 * Address: 0x000054C0 */ -#define rx_flr_rss_control1_adr 0x000054C0u +#define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u /* RX Filter Control Register 2 Definitions * Preprocessor definitions for RX Filter Control Register 2 * Address: 0x00005104 */ -#define rx_flr_control2_adr 0x00005104u +#define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u /* tx tx dma debug control [1f:0] bitfield definitions * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". @@ -459,24 +464,24 @@ */ /* register address for bitfield tx dma debug control [1f:0] */ -#define tdm_tx_dma_debug_ctl_adr 0x00008920 +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 /* bitmask for bitfield tx dma debug control [1f:0] */ -#define tdm_tx_dma_debug_ctl_msk 0xffffffff +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff /* inverted bitmask for bitfield tx dma debug control [1f:0] */ -#define tdm_tx_dma_debug_ctl_mskn 0x00000000 +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 /* lower bit position of bitfield tx dma debug control [1f:0] */ -#define tdm_tx_dma_debug_ctl_shift 0 +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 /* width of bitfield tx dma debug control [1f:0] */ -#define tdm_tx_dma_debug_ctl_width 32 +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 /* default value of bitfield tx dma debug control [1f:0] */ -#define tdm_tx_dma_debug_ctl_default 0x0 +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 /* tx dma descriptor base address lsw definitions * preprocessor definitions for tx dma descriptor base address lsw * base address: 0x00007c00 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] */ -#define tx_dma_desc_base_addrlsw_adr(descriptor) \ +#define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ (0x00007c00u + (descriptor) * 0x40) /* tx dma descriptor tail pointer register definitions @@ -484,7 +489,8 @@ * base address: 0x00007c10 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] */ -#define tx_dma_desc_tail_ptr_adr(descriptor) (0x00007c10u + (descriptor) * 0x40) +#define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ + (0x00007c10u + (descriptor) * 0x40) /* rx dma_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "dma_sys_loopback". @@ -492,17 +498,17 @@ */ /* register address for bitfield dma_sys_loopback */ -#define rpb_dma_sys_lbk_adr 0x00005000 +#define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 /* bitmask for bitfield dma_sys_loopback */ -#define rpb_dma_sys_lbk_msk 0x00000040 +#define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 /* inverted bitmask for bitfield dma_sys_loopback */ -#define rpb_dma_sys_lbk_mskn 0xffffffbf +#define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf /* lower bit position of bitfield dma_sys_loopback */ -#define rpb_dma_sys_lbk_shift 6 +#define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 /* width of bitfield dma_sys_loopback */ -#define rpb_dma_sys_lbk_width 1 +#define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 /* default value of bitfield dma_sys_loopback */ -#define rpb_dma_sys_lbk_default 0x0 +#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 /* rx rx_tc_mode bitfield definitions * preprocessor definitions for the bitfield "rx_tc_mode". @@ -510,17 +516,17 @@ */ /* register address for bitfield rx_tc_mode */ -#define rpb_rpf_rx_tc_mode_adr 0x00005700 +#define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 /* bitmask for bitfield rx_tc_mode */ -#define rpb_rpf_rx_tc_mode_msk 0x00000100 +#define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 /* inverted bitmask for bitfield rx_tc_mode */ -#define rpb_rpf_rx_tc_mode_mskn 0xfffffeff +#define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff /* lower bit position of bitfield rx_tc_mode */ -#define rpb_rpf_rx_tc_mode_shift 8 +#define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 /* width of bitfield rx_tc_mode */ -#define rpb_rpf_rx_tc_mode_width 1 +#define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 /* default value of bitfield rx_tc_mode */ -#define rpb_rpf_rx_tc_mode_default 0x0 +#define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 /* rx rx_buf_en bitfield definitions * preprocessor definitions for the bitfield "rx_buf_en". @@ -528,17 +534,17 @@ */ /* register address for bitfield rx_buf_en */ -#define rpb_rx_buf_en_adr 0x00005700 +#define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 /* bitmask for bitfield rx_buf_en */ -#define rpb_rx_buf_en_msk 0x00000001 +#define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 /* inverted bitmask for bitfield rx_buf_en */ -#define rpb_rx_buf_en_mskn 0xfffffffe +#define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe /* lower bit position of bitfield rx_buf_en */ -#define rpb_rx_buf_en_shift 0 +#define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 /* width of bitfield rx_buf_en */ -#define rpb_rx_buf_en_width 1 +#define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 /* default value of bitfield rx_buf_en */ -#define rpb_rx_buf_en_default 0x0 +#define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 /* rx rx{b}_hi_thresh[d:0] bitfield definitions * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". @@ -547,17 +553,17 @@ */ /* register address for bitfield rx{b}_hi_thresh[d:0] */ -#define rpb_rxbhi_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10) +#define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ -#define rpb_rxbhi_thresh_msk 0x3fff0000 +#define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ -#define rpb_rxbhi_thresh_mskn 0xc000ffff +#define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ -#define rpb_rxbhi_thresh_shift 16 +#define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 /* width of bitfield rx{b}_hi_thresh[d:0] */ -#define rpb_rxbhi_thresh_width 14 +#define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 /* default value of bitfield rx{b}_hi_thresh[d:0] */ -#define rpb_rxbhi_thresh_default 0x0 +#define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 /* rx rx{b}_lo_thresh[d:0] bitfield definitions * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". @@ -566,17 +572,17 @@ */ /* register address for bitfield rx{b}_lo_thresh[d:0] */ -#define rpb_rxblo_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10) +#define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ -#define rpb_rxblo_thresh_msk 0x00003fff +#define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ -#define rpb_rxblo_thresh_mskn 0xffffc000 +#define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ -#define rpb_rxblo_thresh_shift 0 +#define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 /* width of bitfield rx{b}_lo_thresh[d:0] */ -#define rpb_rxblo_thresh_width 14 +#define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 /* default value of bitfield rx{b}_lo_thresh[d:0] */ -#define rpb_rxblo_thresh_default 0x0 +#define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 /* rx rx_fc_mode[1:0] bitfield definitions * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". @@ -584,17 +590,17 @@ */ /* register address for bitfield rx_fc_mode[1:0] */ -#define rpb_rx_fc_mode_adr 0x00005700 +#define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 /* bitmask for bitfield rx_fc_mode[1:0] */ -#define rpb_rx_fc_mode_msk 0x00000030 +#define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ -#define rpb_rx_fc_mode_mskn 0xffffffcf +#define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf /* lower bit position of bitfield rx_fc_mode[1:0] */ -#define rpb_rx_fc_mode_shift 4 +#define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 /* width of bitfield rx_fc_mode[1:0] */ -#define rpb_rx_fc_mode_width 2 +#define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 /* default value of bitfield rx_fc_mode[1:0] */ -#define rpb_rx_fc_mode_default 0x0 +#define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 /* rx rx{b}_buf_size[8:0] bitfield definitions * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". @@ -603,17 +609,17 @@ */ /* register address for bitfield rx{b}_buf_size[8:0] */ -#define rpb_rxbbuf_size_adr(buffer) (0x00005710 + (buffer) * 0x10) +#define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) /* bitmask for bitfield rx{b}_buf_size[8:0] */ -#define rpb_rxbbuf_size_msk 0x000001ff +#define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ -#define rpb_rxbbuf_size_mskn 0xfffffe00 +#define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ -#define rpb_rxbbuf_size_shift 0 +#define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 /* width of bitfield rx{b}_buf_size[8:0] */ -#define rpb_rxbbuf_size_width 9 +#define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 /* default value of bitfield rx{b}_buf_size[8:0] */ -#define rpb_rxbbuf_size_default 0x0 +#define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 /* rx rx{b}_xoff_en bitfield definitions * preprocessor definitions for the bitfield "rx{b}_xoff_en". @@ -622,17 +628,17 @@ */ /* register address for bitfield rx{b}_xoff_en */ -#define rpb_rxbxoff_en_adr(buffer) (0x00005714 + (buffer) * 0x10) +#define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) /* bitmask for bitfield rx{b}_xoff_en */ -#define rpb_rxbxoff_en_msk 0x80000000 +#define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 /* inverted bitmask for bitfield rx{b}_xoff_en */ -#define rpb_rxbxoff_en_mskn 0x7fffffff +#define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff /* lower bit position of bitfield rx{b}_xoff_en */ -#define rpb_rxbxoff_en_shift 31 +#define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 /* width of bitfield rx{b}_xoff_en */ -#define rpb_rxbxoff_en_width 1 +#define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 /* default value of bitfield rx{b}_xoff_en */ -#define rpb_rxbxoff_en_default 0x0 +#define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 /* rx l2_bc_thresh[f:0] bitfield definitions * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". @@ -640,17 +646,17 @@ */ /* register address for bitfield l2_bc_thresh[f:0] */ -#define rpfl2bc_thresh_adr 0x00005100 +#define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 /* bitmask for bitfield l2_bc_thresh[f:0] */ -#define rpfl2bc_thresh_msk 0xffff0000 +#define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ -#define rpfl2bc_thresh_mskn 0x0000ffff +#define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff /* lower bit position of bitfield l2_bc_thresh[f:0] */ -#define rpfl2bc_thresh_shift 16 +#define HW_ATL_RPFL2BC_THRESH_SHIFT 16 /* width of bitfield l2_bc_thresh[f:0] */ -#define rpfl2bc_thresh_width 16 +#define HW_ATL_RPFL2BC_THRESH_WIDTH 16 /* default value of bitfield l2_bc_thresh[f:0] */ -#define rpfl2bc_thresh_default 0x0 +#define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 /* rx l2_bc_en bitfield definitions * preprocessor definitions for the bitfield "l2_bc_en". @@ -658,17 +664,17 @@ */ /* register address for bitfield l2_bc_en */ -#define rpfl2bc_en_adr 0x00005100 +#define HW_ATL_RPFL2BC_EN_ADR 0x00005100 /* bitmask for bitfield l2_bc_en */ -#define rpfl2bc_en_msk 0x00000001 +#define HW_ATL_RPFL2BC_EN_MSK 0x00000001 /* inverted bitmask for bitfield l2_bc_en */ -#define rpfl2bc_en_mskn 0xfffffffe +#define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe /* lower bit position of bitfield l2_bc_en */ -#define rpfl2bc_en_shift 0 +#define HW_ATL_RPFL2BC_EN_SHIFT 0 /* width of bitfield l2_bc_en */ -#define rpfl2bc_en_width 1 +#define HW_ATL_RPFL2BC_EN_WIDTH 1 /* default value of bitfield l2_bc_en */ -#define rpfl2bc_en_default 0x0 +#define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 /* rx l2_bc_act[2:0] bitfield definitions * preprocessor definitions for the bitfield "l2_bc_act[2:0]". @@ -676,17 +682,17 @@ */ /* register address for bitfield l2_bc_act[2:0] */ -#define rpfl2bc_act_adr 0x00005100 +#define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 /* bitmask for bitfield l2_bc_act[2:0] */ -#define rpfl2bc_act_msk 0x00007000 +#define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 /* inverted bitmask for bitfield l2_bc_act[2:0] */ -#define rpfl2bc_act_mskn 0xffff8fff +#define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff /* lower bit position of bitfield l2_bc_act[2:0] */ -#define rpfl2bc_act_shift 12 +#define HW_ATL_RPFL2BC_ACT_SHIFT 12 /* width of bitfield l2_bc_act[2:0] */ -#define rpfl2bc_act_width 3 +#define HW_ATL_RPFL2BC_ACT_WIDTH 3 /* default value of bitfield l2_bc_act[2:0] */ -#define rpfl2bc_act_default 0x0 +#define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 /* rx l2_mc_en{f} bitfield definitions * preprocessor definitions for the bitfield "l2_mc_en{f}". @@ -695,17 +701,17 @@ */ /* register address for bitfield l2_mc_en{f} */ -#define rpfl2mc_enf_adr(filter) (0x00005250 + (filter) * 0x4) +#define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) /* bitmask for bitfield l2_mc_en{f} */ -#define rpfl2mc_enf_msk 0x80000000 +#define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 /* inverted bitmask for bitfield l2_mc_en{f} */ -#define rpfl2mc_enf_mskn 0x7fffffff +#define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff /* lower bit position of bitfield l2_mc_en{f} */ -#define rpfl2mc_enf_shift 31 +#define HW_ATL_RPFL2MC_ENF_SHIFT 31 /* width of bitfield l2_mc_en{f} */ -#define rpfl2mc_enf_width 1 +#define HW_ATL_RPFL2MC_ENF_WIDTH 1 /* default value of bitfield l2_mc_en{f} */ -#define rpfl2mc_enf_default 0x0 +#define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 /* rx l2_promis_mode bitfield definitions * preprocessor definitions for the bitfield "l2_promis_mode". @@ -713,17 +719,17 @@ */ /* register address for bitfield l2_promis_mode */ -#define rpfl2promis_mode_adr 0x00005100 +#define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 /* bitmask for bitfield l2_promis_mode */ -#define rpfl2promis_mode_msk 0x00000008 +#define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 /* inverted bitmask for bitfield l2_promis_mode */ -#define rpfl2promis_mode_mskn 0xfffffff7 +#define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 /* lower bit position of bitfield l2_promis_mode */ -#define rpfl2promis_mode_shift 3 +#define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 /* width of bitfield l2_promis_mode */ -#define rpfl2promis_mode_width 1 +#define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 /* default value of bitfield l2_promis_mode */ -#define rpfl2promis_mode_default 0x0 +#define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 /* rx l2_uc_act{f}[2:0] bitfield definitions * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". @@ -732,17 +738,17 @@ */ /* register address for bitfield l2_uc_act{f}[2:0] */ -#define rpfl2uc_actf_adr(filter) (0x00005114 + (filter) * 0x8) +#define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) /* bitmask for bitfield l2_uc_act{f}[2:0] */ -#define rpfl2uc_actf_msk 0x00070000 +#define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ -#define rpfl2uc_actf_mskn 0xfff8ffff +#define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff /* lower bit position of bitfield l2_uc_act{f}[2:0] */ -#define rpfl2uc_actf_shift 16 +#define HW_ATL_RPFL2UC_ACTF_SHIFT 16 /* width of bitfield l2_uc_act{f}[2:0] */ -#define rpfl2uc_actf_width 3 +#define HW_ATL_RPFL2UC_ACTF_WIDTH 3 /* default value of bitfield l2_uc_act{f}[2:0] */ -#define rpfl2uc_actf_default 0x0 +#define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 /* rx l2_uc_en{f} bitfield definitions * preprocessor definitions for the bitfield "l2_uc_en{f}". @@ -751,26 +757,26 @@ */ /* register address for bitfield l2_uc_en{f} */ -#define rpfl2uc_enf_adr(filter) (0x00005114 + (filter) * 0x8) +#define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) /* bitmask for bitfield l2_uc_en{f} */ -#define rpfl2uc_enf_msk 0x80000000 +#define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 /* inverted bitmask for bitfield l2_uc_en{f} */ -#define rpfl2uc_enf_mskn 0x7fffffff +#define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff /* lower bit position of bitfield l2_uc_en{f} */ -#define rpfl2uc_enf_shift 31 +#define HW_ATL_RPFL2UC_ENF_SHIFT 31 /* width of bitfield l2_uc_en{f} */ -#define rpfl2uc_enf_width 1 +#define HW_ATL_RPFL2UC_ENF_WIDTH 1 /* default value of bitfield l2_uc_en{f} */ -#define rpfl2uc_enf_default 0x0 +#define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ -#define rpfl2uc_daflsw_adr(filter) (0x00005110 + (filter) * 0x8) +#define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) /* register address for bitfield l2_uc_da{f}_msw[f:0] */ -#define rpfl2uc_dafmsw_adr(filter) (0x00005114 + (filter) * 0x8) +#define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ -#define rpfl2uc_dafmsw_msk 0x0000ffff +#define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ -#define rpfl2uc_dafmsw_shift 0 +#define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 /* rx l2_mc_accept_all bitfield definitions * Preprocessor definitions for the bitfield "l2_mc_accept_all". @@ -778,22 +784,22 @@ */ /* Register address for bitfield l2_mc_accept_all */ -#define rpfl2mc_accept_all_adr 0x00005270 +#define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 /* Bitmask for bitfield l2_mc_accept_all */ -#define rpfl2mc_accept_all_msk 0x00004000 +#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 /* Inverted bitmask for bitfield l2_mc_accept_all */ -#define rpfl2mc_accept_all_mskn 0xFFFFBFFF +#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF /* Lower bit position of bitfield l2_mc_accept_all */ -#define rpfl2mc_accept_all_shift 14 +#define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 /* Width of bitfield l2_mc_accept_all */ -#define rpfl2mc_accept_all_width 1 +#define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 /* Default value of bitfield l2_mc_accept_all */ -#define rpfl2mc_accept_all_default 0x0 +#define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 /* width of bitfield rx_tc_up{t}[2:0] */ -#define rpf_rpb_rx_tc_upt_width 3 +#define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 /* default value of bitfield rx_tc_up{t}[2:0] */ -#define rpf_rpb_rx_tc_upt_default 0x0 +#define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 /* rx rss_key_addr[4:0] bitfield definitions * preprocessor definitions for the bitfield "rss_key_addr[4:0]". @@ -801,17 +807,17 @@ */ /* register address for bitfield rss_key_addr[4:0] */ -#define rpf_rss_key_addr_adr 0x000054d0 +#define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 /* bitmask for bitfield rss_key_addr[4:0] */ -#define rpf_rss_key_addr_msk 0x0000001f +#define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f /* inverted bitmask for bitfield rss_key_addr[4:0] */ -#define rpf_rss_key_addr_mskn 0xffffffe0 +#define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 /* lower bit position of bitfield rss_key_addr[4:0] */ -#define rpf_rss_key_addr_shift 0 +#define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 /* width of bitfield rss_key_addr[4:0] */ -#define rpf_rss_key_addr_width 5 +#define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 /* default value of bitfield rss_key_addr[4:0] */ -#define rpf_rss_key_addr_default 0x0 +#define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 /* rx rss_key_wr_data[1f:0] bitfield definitions * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". @@ -819,17 +825,17 @@ */ /* register address for bitfield rss_key_wr_data[1f:0] */ -#define rpf_rss_key_wr_data_adr 0x000054d4 +#define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 /* bitmask for bitfield rss_key_wr_data[1f:0] */ -#define rpf_rss_key_wr_data_msk 0xffffffff +#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ -#define rpf_rss_key_wr_data_mskn 0x00000000 +#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ -#define rpf_rss_key_wr_data_shift 0 +#define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 /* width of bitfield rss_key_wr_data[1f:0] */ -#define rpf_rss_key_wr_data_width 32 +#define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 /* default value of bitfield rss_key_wr_data[1f:0] */ -#define rpf_rss_key_wr_data_default 0x0 +#define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 /* rx rss_key_wr_en_i bitfield definitions * preprocessor definitions for the bitfield "rss_key_wr_en_i". @@ -837,17 +843,17 @@ */ /* register address for bitfield rss_key_wr_en_i */ -#define rpf_rss_key_wr_eni_adr 0x000054d0 +#define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 /* bitmask for bitfield rss_key_wr_en_i */ -#define rpf_rss_key_wr_eni_msk 0x00000020 +#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 /* inverted bitmask for bitfield rss_key_wr_en_i */ -#define rpf_rss_key_wr_eni_mskn 0xffffffdf +#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf /* lower bit position of bitfield rss_key_wr_en_i */ -#define rpf_rss_key_wr_eni_shift 5 +#define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 /* width of bitfield rss_key_wr_en_i */ -#define rpf_rss_key_wr_eni_width 1 +#define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 /* default value of bitfield rss_key_wr_en_i */ -#define rpf_rss_key_wr_eni_default 0x0 +#define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 /* rx rss_redir_addr[3:0] bitfield definitions * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". @@ -855,17 +861,17 @@ */ /* register address for bitfield rss_redir_addr[3:0] */ -#define rpf_rss_redir_addr_adr 0x000054e0 +#define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 /* bitmask for bitfield rss_redir_addr[3:0] */ -#define rpf_rss_redir_addr_msk 0x0000000f +#define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f /* inverted bitmask for bitfield rss_redir_addr[3:0] */ -#define rpf_rss_redir_addr_mskn 0xfffffff0 +#define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 /* lower bit position of bitfield rss_redir_addr[3:0] */ -#define rpf_rss_redir_addr_shift 0 +#define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 /* width of bitfield rss_redir_addr[3:0] */ -#define rpf_rss_redir_addr_width 4 +#define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 /* default value of bitfield rss_redir_addr[3:0] */ -#define rpf_rss_redir_addr_default 0x0 +#define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 /* rx rss_redir_wr_data[f:0] bitfield definitions * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". @@ -873,17 +879,17 @@ */ /* register address for bitfield rss_redir_wr_data[f:0] */ -#define rpf_rss_redir_wr_data_adr 0x000054e4 +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 /* bitmask for bitfield rss_redir_wr_data[f:0] */ -#define rpf_rss_redir_wr_data_msk 0x0000ffff +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ -#define rpf_rss_redir_wr_data_mskn 0xffff0000 +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ -#define rpf_rss_redir_wr_data_shift 0 +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 /* width of bitfield rss_redir_wr_data[f:0] */ -#define rpf_rss_redir_wr_data_width 16 +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 /* default value of bitfield rss_redir_wr_data[f:0] */ -#define rpf_rss_redir_wr_data_default 0x0 +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 /* rx rss_redir_wr_en_i bitfield definitions * preprocessor definitions for the bitfield "rss_redir_wr_en_i". @@ -891,17 +897,17 @@ */ /* register address for bitfield rss_redir_wr_en_i */ -#define rpf_rss_redir_wr_eni_adr 0x000054e0 +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 /* bitmask for bitfield rss_redir_wr_en_i */ -#define rpf_rss_redir_wr_eni_msk 0x00000010 +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 /* inverted bitmask for bitfield rss_redir_wr_en_i */ -#define rpf_rss_redir_wr_eni_mskn 0xffffffef +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef /* lower bit position of bitfield rss_redir_wr_en_i */ -#define rpf_rss_redir_wr_eni_shift 4 +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 /* width of bitfield rss_redir_wr_en_i */ -#define rpf_rss_redir_wr_eni_width 1 +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 /* default value of bitfield rss_redir_wr_en_i */ -#define rpf_rss_redir_wr_eni_default 0x0 +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 /* rx tpo_rpf_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". @@ -909,17 +915,17 @@ */ /* register address for bitfield tpo_rpf_sys_loopback */ -#define rpf_tpo_rpf_sys_lbk_adr 0x00005000 +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 /* bitmask for bitfield tpo_rpf_sys_loopback */ -#define rpf_tpo_rpf_sys_lbk_msk 0x00000100 +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ -#define rpf_tpo_rpf_sys_lbk_mskn 0xfffffeff +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff /* lower bit position of bitfield tpo_rpf_sys_loopback */ -#define rpf_tpo_rpf_sys_lbk_shift 8 +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 /* width of bitfield tpo_rpf_sys_loopback */ -#define rpf_tpo_rpf_sys_lbk_width 1 +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 /* default value of bitfield tpo_rpf_sys_loopback */ -#define rpf_tpo_rpf_sys_lbk_default 0x0 +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 /* rx vl_inner_tpid[f:0] bitfield definitions * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". @@ -927,17 +933,17 @@ */ /* register address for bitfield vl_inner_tpid[f:0] */ -#define rpf_vl_inner_tpid_adr 0x00005284 +#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 /* bitmask for bitfield vl_inner_tpid[f:0] */ -#define rpf_vl_inner_tpid_msk 0x0000ffff +#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ -#define rpf_vl_inner_tpid_mskn 0xffff0000 +#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 /* lower bit position of bitfield vl_inner_tpid[f:0] */ -#define rpf_vl_inner_tpid_shift 0 +#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 /* width of bitfield vl_inner_tpid[f:0] */ -#define rpf_vl_inner_tpid_width 16 +#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 /* default value of bitfield vl_inner_tpid[f:0] */ -#define rpf_vl_inner_tpid_default 0x8100 +#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 /* rx vl_outer_tpid[f:0] bitfield definitions * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". @@ -945,17 +951,17 @@ */ /* register address for bitfield vl_outer_tpid[f:0] */ -#define rpf_vl_outer_tpid_adr 0x00005284 +#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 /* bitmask for bitfield vl_outer_tpid[f:0] */ -#define rpf_vl_outer_tpid_msk 0xffff0000 +#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ -#define rpf_vl_outer_tpid_mskn 0x0000ffff +#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff /* lower bit position of bitfield vl_outer_tpid[f:0] */ -#define rpf_vl_outer_tpid_shift 16 +#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 /* width of bitfield vl_outer_tpid[f:0] */ -#define rpf_vl_outer_tpid_width 16 +#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 /* default value of bitfield vl_outer_tpid[f:0] */ -#define rpf_vl_outer_tpid_default 0x88a8 +#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 /* rx vl_promis_mode bitfield definitions * preprocessor definitions for the bitfield "vl_promis_mode". @@ -963,17 +969,17 @@ */ /* register address for bitfield vl_promis_mode */ -#define rpf_vl_promis_mode_adr 0x00005280 +#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 /* bitmask for bitfield vl_promis_mode */ -#define rpf_vl_promis_mode_msk 0x00000002 +#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 /* inverted bitmask for bitfield vl_promis_mode */ -#define rpf_vl_promis_mode_mskn 0xfffffffd +#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd /* lower bit position of bitfield vl_promis_mode */ -#define rpf_vl_promis_mode_shift 1 +#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 /* width of bitfield vl_promis_mode */ -#define rpf_vl_promis_mode_width 1 +#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 /* default value of bitfield vl_promis_mode */ -#define rpf_vl_promis_mode_default 0x0 +#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 /* RX vl_accept_untagged_mode Bitfield Definitions * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". @@ -981,17 +987,17 @@ */ /* Register address for bitfield vl_accept_untagged_mode */ -#define rpf_vl_accept_untagged_mode_adr 0x00005280 +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 /* Bitmask for bitfield vl_accept_untagged_mode */ -#define rpf_vl_accept_untagged_mode_msk 0x00000004 +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ -#define rpf_vl_accept_untagged_mode_mskn 0xFFFFFFFB +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB /* Lower bit position of bitfield vl_accept_untagged_mode */ -#define rpf_vl_accept_untagged_mode_shift 2 +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 /* Width of bitfield vl_accept_untagged_mode */ -#define rpf_vl_accept_untagged_mode_width 1 +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 /* Default value of bitfield vl_accept_untagged_mode */ -#define rpf_vl_accept_untagged_mode_default 0x0 +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 /* rX vl_untagged_act[2:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". @@ -999,17 +1005,17 @@ */ /* Register address for bitfield vl_untagged_act[2:0] */ -#define rpf_vl_untagged_act_adr 0x00005280 +#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 /* Bitmask for bitfield vl_untagged_act[2:0] */ -#define rpf_vl_untagged_act_msk 0x00000038 +#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ -#define rpf_vl_untagged_act_mskn 0xFFFFFFC7 +#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 /* Lower bit position of bitfield vl_untagged_act[2:0] */ -#define rpf_vl_untagged_act_shift 3 +#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 /* Width of bitfield vl_untagged_act[2:0] */ -#define rpf_vl_untagged_act_width 3 +#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 /* Default value of bitfield vl_untagged_act[2:0] */ -#define rpf_vl_untagged_act_default 0x0 +#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 /* RX vl_en{F} Bitfield Definitions * Preprocessor definitions for the bitfield "vl_en{F}". @@ -1018,17 +1024,17 @@ */ /* Register address for bitfield vl_en{F} */ -#define rpf_vl_en_f_adr(filter) (0x00005290 + (filter) * 0x4) +#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) /* Bitmask for bitfield vl_en{F} */ -#define rpf_vl_en_f_msk 0x80000000 +#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 /* Inverted bitmask for bitfield vl_en{F} */ -#define rpf_vl_en_f_mskn 0x7FFFFFFF +#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF /* Lower bit position of bitfield vl_en{F} */ -#define rpf_vl_en_f_shift 31 +#define HW_ATL_RPF_VL_EN_F_SHIFT 31 /* Width of bitfield vl_en{F} */ -#define rpf_vl_en_f_width 1 +#define HW_ATL_RPF_VL_EN_F_WIDTH 1 /* Default value of bitfield vl_en{F} */ -#define rpf_vl_en_f_default 0x0 +#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 /* RX vl_act{F}[2:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". @@ -1037,17 +1043,17 @@ */ /* Register address for bitfield vl_act{F}[2:0] */ -#define rpf_vl_act_f_adr(filter) (0x00005290 + (filter) * 0x4) +#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) /* Bitmask for bitfield vl_act{F}[2:0] */ -#define rpf_vl_act_f_msk 0x00070000 +#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ -#define rpf_vl_act_f_mskn 0xFFF8FFFF +#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF /* Lower bit position of bitfield vl_act{F}[2:0] */ -#define rpf_vl_act_f_shift 16 +#define HW_ATL_RPF_VL_ACT_F_SHIFT 16 /* Width of bitfield vl_act{F}[2:0] */ -#define rpf_vl_act_f_width 3 +#define HW_ATL_RPF_VL_ACT_F_WIDTH 3 /* Default value of bitfield vl_act{F}[2:0] */ -#define rpf_vl_act_f_default 0x0 +#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 /* RX vl_id{F}[B:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". @@ -1056,17 +1062,17 @@ */ /* Register address for bitfield vl_id{F}[B:0] */ -#define rpf_vl_id_f_adr(filter) (0x00005290 + (filter) * 0x4) +#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) /* Bitmask for bitfield vl_id{F}[B:0] */ -#define rpf_vl_id_f_msk 0x00000FFF +#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF /* Inverted bitmask for bitfield vl_id{F}[B:0] */ -#define rpf_vl_id_f_mskn 0xFFFFF000 +#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 /* Lower bit position of bitfield vl_id{F}[B:0] */ -#define rpf_vl_id_f_shift 0 +#define HW_ATL_RPF_VL_ID_F_SHIFT 0 /* Width of bitfield vl_id{F}[B:0] */ -#define rpf_vl_id_f_width 12 +#define HW_ATL_RPF_VL_ID_F_WIDTH 12 /* Default value of bitfield vl_id{F}[B:0] */ -#define rpf_vl_id_f_default 0x0 +#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 /* RX et_en{F} Bitfield Definitions * Preprocessor definitions for the bitfield "et_en{F}". @@ -1075,17 +1081,17 @@ */ /* Register address for bitfield et_en{F} */ -#define rpf_et_en_f_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4) /* Bitmask for bitfield et_en{F} */ -#define rpf_et_en_f_msk 0x80000000 +#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000 /* Inverted bitmask for bitfield et_en{F} */ -#define rpf_et_en_f_mskn 0x7FFFFFFF +#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF /* Lower bit position of bitfield et_en{F} */ -#define rpf_et_en_f_shift 31 +#define HW_ATL_RPF_ET_EN_F_SHIFT 31 /* Width of bitfield et_en{F} */ -#define rpf_et_en_f_width 1 +#define HW_ATL_RPF_ET_EN_F_WIDTH 1 /* Default value of bitfield et_en{F} */ -#define rpf_et_en_f_default 0x0 +#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0 /* rx et_en{f} bitfield definitions * preprocessor definitions for the bitfield "et_en{f}". @@ -1094,17 +1100,17 @@ */ /* register address for bitfield et_en{f} */ -#define rpf_et_enf_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_en{f} */ -#define rpf_et_enf_msk 0x80000000 +#define HW_ATL_RPF_ET_ENF_MSK 0x80000000 /* inverted bitmask for bitfield et_en{f} */ -#define rpf_et_enf_mskn 0x7fffffff +#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff /* lower bit position of bitfield et_en{f} */ -#define rpf_et_enf_shift 31 +#define HW_ATL_RPF_ET_ENF_SHIFT 31 /* width of bitfield et_en{f} */ -#define rpf_et_enf_width 1 +#define HW_ATL_RPF_ET_ENF_WIDTH 1 /* default value of bitfield et_en{f} */ -#define rpf_et_enf_default 0x0 +#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 /* rx et_up{f}_en bitfield definitions * preprocessor definitions for the bitfield "et_up{f}_en". @@ -1113,17 +1119,17 @@ */ /* register address for bitfield et_up{f}_en */ -#define rpf_et_upfen_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_up{f}_en */ -#define rpf_et_upfen_msk 0x40000000 +#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 /* inverted bitmask for bitfield et_up{f}_en */ -#define rpf_et_upfen_mskn 0xbfffffff +#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff /* lower bit position of bitfield et_up{f}_en */ -#define rpf_et_upfen_shift 30 +#define HW_ATL_RPF_ET_UPFEN_SHIFT 30 /* width of bitfield et_up{f}_en */ -#define rpf_et_upfen_width 1 +#define HW_ATL_RPF_ET_UPFEN_WIDTH 1 /* default value of bitfield et_up{f}_en */ -#define rpf_et_upfen_default 0x0 +#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 /* rx et_rxq{f}_en bitfield definitions * preprocessor definitions for the bitfield "et_rxq{f}_en". @@ -1132,17 +1138,17 @@ */ /* register address for bitfield et_rxq{f}_en */ -#define rpf_et_rxqfen_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_rxq{f}_en */ -#define rpf_et_rxqfen_msk 0x20000000 +#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 /* inverted bitmask for bitfield et_rxq{f}_en */ -#define rpf_et_rxqfen_mskn 0xdfffffff +#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff /* lower bit position of bitfield et_rxq{f}_en */ -#define rpf_et_rxqfen_shift 29 +#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 /* width of bitfield et_rxq{f}_en */ -#define rpf_et_rxqfen_width 1 +#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 /* default value of bitfield et_rxq{f}_en */ -#define rpf_et_rxqfen_default 0x0 +#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 /* rx et_up{f}[2:0] bitfield definitions * preprocessor definitions for the bitfield "et_up{f}[2:0]". @@ -1151,17 +1157,17 @@ */ /* register address for bitfield et_up{f}[2:0] */ -#define rpf_et_upf_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_up{f}[2:0] */ -#define rpf_et_upf_msk 0x1c000000 +#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 /* inverted bitmask for bitfield et_up{f}[2:0] */ -#define rpf_et_upf_mskn 0xe3ffffff +#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff /* lower bit position of bitfield et_up{f}[2:0] */ -#define rpf_et_upf_shift 26 +#define HW_ATL_RPF_ET_UPF_SHIFT 26 /* width of bitfield et_up{f}[2:0] */ -#define rpf_et_upf_width 3 +#define HW_ATL_RPF_ET_UPF_WIDTH 3 /* default value of bitfield et_up{f}[2:0] */ -#define rpf_et_upf_default 0x0 +#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 /* rx et_rxq{f}[4:0] bitfield definitions * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". @@ -1170,17 +1176,17 @@ */ /* register address for bitfield et_rxq{f}[4:0] */ -#define rpf_et_rxqf_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_rxq{f}[4:0] */ -#define rpf_et_rxqf_msk 0x01f00000 +#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ -#define rpf_et_rxqf_mskn 0xfe0fffff +#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff /* lower bit position of bitfield et_rxq{f}[4:0] */ -#define rpf_et_rxqf_shift 20 +#define HW_ATL_RPF_ET_RXQF_SHIFT 20 /* width of bitfield et_rxq{f}[4:0] */ -#define rpf_et_rxqf_width 5 +#define HW_ATL_RPF_ET_RXQF_WIDTH 5 /* default value of bitfield et_rxq{f}[4:0] */ -#define rpf_et_rxqf_default 0x0 +#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 /* rx et_mng_rxq{f} bitfield definitions * preprocessor definitions for the bitfield "et_mng_rxq{f}". @@ -1189,17 +1195,17 @@ */ /* register address for bitfield et_mng_rxq{f} */ -#define rpf_et_mng_rxqf_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_mng_rxq{f} */ -#define rpf_et_mng_rxqf_msk 0x00080000 +#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 /* inverted bitmask for bitfield et_mng_rxq{f} */ -#define rpf_et_mng_rxqf_mskn 0xfff7ffff +#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff /* lower bit position of bitfield et_mng_rxq{f} */ -#define rpf_et_mng_rxqf_shift 19 +#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 /* width of bitfield et_mng_rxq{f} */ -#define rpf_et_mng_rxqf_width 1 +#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 /* default value of bitfield et_mng_rxq{f} */ -#define rpf_et_mng_rxqf_default 0x0 +#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 /* rx et_act{f}[2:0] bitfield definitions * preprocessor definitions for the bitfield "et_act{f}[2:0]". @@ -1208,17 +1214,17 @@ */ /* register address for bitfield et_act{f}[2:0] */ -#define rpf_et_actf_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_act{f}[2:0] */ -#define rpf_et_actf_msk 0x00070000 +#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 /* inverted bitmask for bitfield et_act{f}[2:0] */ -#define rpf_et_actf_mskn 0xfff8ffff +#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff /* lower bit position of bitfield et_act{f}[2:0] */ -#define rpf_et_actf_shift 16 +#define HW_ATL_RPF_ET_ACTF_SHIFT 16 /* width of bitfield et_act{f}[2:0] */ -#define rpf_et_actf_width 3 +#define HW_ATL_RPF_ET_ACTF_WIDTH 3 /* default value of bitfield et_act{f}[2:0] */ -#define rpf_et_actf_default 0x0 +#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 /* rx et_val{f}[f:0] bitfield definitions * preprocessor definitions for the bitfield "et_val{f}[f:0]". @@ -1227,17 +1233,17 @@ */ /* register address for bitfield et_val{f}[f:0] */ -#define rpf_et_valf_adr(filter) (0x00005300 + (filter) * 0x4) +#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) /* bitmask for bitfield et_val{f}[f:0] */ -#define rpf_et_valf_msk 0x0000ffff +#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff /* inverted bitmask for bitfield et_val{f}[f:0] */ -#define rpf_et_valf_mskn 0xffff0000 +#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 /* lower bit position of bitfield et_val{f}[f:0] */ -#define rpf_et_valf_shift 0 +#define HW_ATL_RPF_ET_VALF_SHIFT 0 /* width of bitfield et_val{f}[f:0] */ -#define rpf_et_valf_width 16 +#define HW_ATL_RPF_ET_VALF_WIDTH 16 /* default value of bitfield et_val{f}[f:0] */ -#define rpf_et_valf_default 0x0 +#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 /* rx ipv4_chk_en bitfield definitions * preprocessor definitions for the bitfield "ipv4_chk_en". @@ -1245,17 +1251,17 @@ */ /* register address for bitfield ipv4_chk_en */ -#define rpo_ipv4chk_en_adr 0x00005580 +#define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 /* bitmask for bitfield ipv4_chk_en */ -#define rpo_ipv4chk_en_msk 0x00000002 +#define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 /* inverted bitmask for bitfield ipv4_chk_en */ -#define rpo_ipv4chk_en_mskn 0xfffffffd +#define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd /* lower bit position of bitfield ipv4_chk_en */ -#define rpo_ipv4chk_en_shift 1 +#define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 /* width of bitfield ipv4_chk_en */ -#define rpo_ipv4chk_en_width 1 +#define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 /* default value of bitfield ipv4_chk_en */ -#define rpo_ipv4chk_en_default 0x0 +#define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 /* rx desc{d}_vl_strip bitfield definitions * preprocessor definitions for the bitfield "desc{d}_vl_strip". @@ -1264,17 +1270,18 @@ */ /* register address for bitfield desc{d}_vl_strip */ -#define rpo_descdvl_strip_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) +#define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ + (0x00005b08 + (descriptor) * 0x20) /* bitmask for bitfield desc{d}_vl_strip */ -#define rpo_descdvl_strip_msk 0x20000000 +#define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 /* inverted bitmask for bitfield desc{d}_vl_strip */ -#define rpo_descdvl_strip_mskn 0xdfffffff +#define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff /* lower bit position of bitfield desc{d}_vl_strip */ -#define rpo_descdvl_strip_shift 29 +#define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 /* width of bitfield desc{d}_vl_strip */ -#define rpo_descdvl_strip_width 1 +#define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 /* default value of bitfield desc{d}_vl_strip */ -#define rpo_descdvl_strip_default 0x0 +#define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 /* rx l4_chk_en bitfield definitions * preprocessor definitions for the bitfield "l4_chk_en". @@ -1282,17 +1289,17 @@ */ /* register address for bitfield l4_chk_en */ -#define rpol4chk_en_adr 0x00005580 +#define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 /* bitmask for bitfield l4_chk_en */ -#define rpol4chk_en_msk 0x00000001 +#define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 /* inverted bitmask for bitfield l4_chk_en */ -#define rpol4chk_en_mskn 0xfffffffe +#define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe /* lower bit position of bitfield l4_chk_en */ -#define rpol4chk_en_shift 0 +#define HW_ATL_RPOL4CHK_EN_SHIFT 0 /* width of bitfield l4_chk_en */ -#define rpol4chk_en_width 1 +#define HW_ATL_RPOL4CHK_EN_WIDTH 1 /* default value of bitfield l4_chk_en */ -#define rpol4chk_en_default 0x0 +#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 /* rx reg_res_dsbl bitfield definitions * preprocessor definitions for the bitfield "reg_res_dsbl". @@ -1300,17 +1307,17 @@ */ /* register address for bitfield reg_res_dsbl */ -#define rx_reg_res_dsbl_adr 0x00005000 +#define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 /* bitmask for bitfield reg_res_dsbl */ -#define rx_reg_res_dsbl_msk 0x20000000 +#define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 /* inverted bitmask for bitfield reg_res_dsbl */ -#define rx_reg_res_dsbl_mskn 0xdfffffff +#define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff /* lower bit position of bitfield reg_res_dsbl */ -#define rx_reg_res_dsbl_shift 29 +#define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 /* width of bitfield reg_res_dsbl */ -#define rx_reg_res_dsbl_width 1 +#define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 /* default value of bitfield reg_res_dsbl */ -#define rx_reg_res_dsbl_default 0x1 +#define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 /* tx dca{d}_cpuid[7:0] bitfield definitions * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". @@ -1319,17 +1326,17 @@ */ /* register address for bitfield dca{d}_cpuid[7:0] */ -#define tdm_dcadcpuid_adr(dca) (0x00008400 + (dca) * 0x4) +#define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) /* bitmask for bitfield dca{d}_cpuid[7:0] */ -#define tdm_dcadcpuid_msk 0x000000ff +#define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ -#define tdm_dcadcpuid_mskn 0xffffff00 +#define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ -#define tdm_dcadcpuid_shift 0 +#define HW_ATL_TDM_DCADCPUID_SHIFT 0 /* width of bitfield dca{d}_cpuid[7:0] */ -#define tdm_dcadcpuid_width 8 +#define HW_ATL_TDM_DCADCPUID_WIDTH 8 /* default value of bitfield dca{d}_cpuid[7:0] */ -#define tdm_dcadcpuid_default 0x0 +#define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 /* tx lso_en[1f:0] bitfield definitions * preprocessor definitions for the bitfield "lso_en[1f:0]". @@ -1337,17 +1344,17 @@ */ /* register address for bitfield lso_en[1f:0] */ -#define tdm_lso_en_adr 0x00007810 +#define HW_ATL_TDM_LSO_EN_ADR 0x00007810 /* bitmask for bitfield lso_en[1f:0] */ -#define tdm_lso_en_msk 0xffffffff +#define HW_ATL_TDM_LSO_EN_MSK 0xffffffff /* inverted bitmask for bitfield lso_en[1f:0] */ -#define tdm_lso_en_mskn 0x00000000 +#define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 /* lower bit position of bitfield lso_en[1f:0] */ -#define tdm_lso_en_shift 0 +#define HW_ATL_TDM_LSO_EN_SHIFT 0 /* width of bitfield lso_en[1f:0] */ -#define tdm_lso_en_width 32 +#define HW_ATL_TDM_LSO_EN_WIDTH 32 /* default value of bitfield lso_en[1f:0] */ -#define tdm_lso_en_default 0x0 +#define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 /* tx dca_en bitfield definitions * preprocessor definitions for the bitfield "dca_en". @@ -1355,17 +1362,17 @@ */ /* register address for bitfield dca_en */ -#define tdm_dca_en_adr 0x00008480 +#define HW_ATL_TDM_DCA_EN_ADR 0x00008480 /* bitmask for bitfield dca_en */ -#define tdm_dca_en_msk 0x80000000 +#define HW_ATL_TDM_DCA_EN_MSK 0x80000000 /* inverted bitmask for bitfield dca_en */ -#define tdm_dca_en_mskn 0x7fffffff +#define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff /* lower bit position of bitfield dca_en */ -#define tdm_dca_en_shift 31 +#define HW_ATL_TDM_DCA_EN_SHIFT 31 /* width of bitfield dca_en */ -#define tdm_dca_en_width 1 +#define HW_ATL_TDM_DCA_EN_WIDTH 1 /* default value of bitfield dca_en */ -#define tdm_dca_en_default 0x1 +#define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 /* tx dca_mode[3:0] bitfield definitions * preprocessor definitions for the bitfield "dca_mode[3:0]". @@ -1373,17 +1380,17 @@ */ /* register address for bitfield dca_mode[3:0] */ -#define tdm_dca_mode_adr 0x00008480 +#define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 /* bitmask for bitfield dca_mode[3:0] */ -#define tdm_dca_mode_msk 0x0000000f +#define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f /* inverted bitmask for bitfield dca_mode[3:0] */ -#define tdm_dca_mode_mskn 0xfffffff0 +#define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 /* lower bit position of bitfield dca_mode[3:0] */ -#define tdm_dca_mode_shift 0 +#define HW_ATL_TDM_DCA_MODE_SHIFT 0 /* width of bitfield dca_mode[3:0] */ -#define tdm_dca_mode_width 4 +#define HW_ATL_TDM_DCA_MODE_WIDTH 4 /* default value of bitfield dca_mode[3:0] */ -#define tdm_dca_mode_default 0x0 +#define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 /* tx dca{d}_desc_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_desc_en". @@ -1392,17 +1399,17 @@ */ /* register address for bitfield dca{d}_desc_en */ -#define tdm_dcaddesc_en_adr(dca) (0x00008400 + (dca) * 0x4) +#define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) /* bitmask for bitfield dca{d}_desc_en */ -#define tdm_dcaddesc_en_msk 0x80000000 +#define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 /* inverted bitmask for bitfield dca{d}_desc_en */ -#define tdm_dcaddesc_en_mskn 0x7fffffff +#define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff /* lower bit position of bitfield dca{d}_desc_en */ -#define tdm_dcaddesc_en_shift 31 +#define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 /* width of bitfield dca{d}_desc_en */ -#define tdm_dcaddesc_en_width 1 +#define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 /* default value of bitfield dca{d}_desc_en */ -#define tdm_dcaddesc_en_default 0x0 +#define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 /* tx desc{d}_en bitfield definitions * preprocessor definitions for the bitfield "desc{d}_en". @@ -1411,17 +1418,17 @@ */ /* register address for bitfield desc{d}_en */ -#define tdm_descden_adr(descriptor) (0x00007c08 + (descriptor) * 0x40) +#define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) /* bitmask for bitfield desc{d}_en */ -#define tdm_descden_msk 0x80000000 +#define HW_ATL_TDM_DESCDEN_MSK 0x80000000 /* inverted bitmask for bitfield desc{d}_en */ -#define tdm_descden_mskn 0x7fffffff +#define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff /* lower bit position of bitfield desc{d}_en */ -#define tdm_descden_shift 31 +#define HW_ATL_TDM_DESCDEN_SHIFT 31 /* width of bitfield desc{d}_en */ -#define tdm_descden_width 1 +#define HW_ATL_TDM_DESCDEN_WIDTH 1 /* default value of bitfield desc{d}_en */ -#define tdm_descden_default 0x0 +#define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 /* tx desc{d}_hd[c:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". @@ -1430,15 +1437,15 @@ */ /* register address for bitfield desc{d}_hd[c:0] */ -#define tdm_descdhd_adr(descriptor) (0x00007c0c + (descriptor) * 0x40) +#define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) /* bitmask for bitfield desc{d}_hd[c:0] */ -#define tdm_descdhd_msk 0x00001fff +#define HW_ATL_TDM_DESCDHD_MSK 0x00001fff /* inverted bitmask for bitfield desc{d}_hd[c:0] */ -#define tdm_descdhd_mskn 0xffffe000 +#define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 /* lower bit position of bitfield desc{d}_hd[c:0] */ -#define tdm_descdhd_shift 0 +#define HW_ATL_TDM_DESCDHD_SHIFT 0 /* width of bitfield desc{d}_hd[c:0] */ -#define tdm_descdhd_width 13 +#define HW_ATL_TDM_DESCDHD_WIDTH 13 /* tx desc{d}_len[9:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_len[9:0]". @@ -1447,17 +1454,17 @@ */ /* register address for bitfield desc{d}_len[9:0] */ -#define tdm_descdlen_adr(descriptor) (0x00007c08 + (descriptor) * 0x40) +#define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) /* bitmask for bitfield desc{d}_len[9:0] */ -#define tdm_descdlen_msk 0x00001ff8 +#define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 /* inverted bitmask for bitfield desc{d}_len[9:0] */ -#define tdm_descdlen_mskn 0xffffe007 +#define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 /* lower bit position of bitfield desc{d}_len[9:0] */ -#define tdm_descdlen_shift 3 +#define HW_ATL_TDM_DESCDLEN_SHIFT 3 /* width of bitfield desc{d}_len[9:0] */ -#define tdm_descdlen_width 10 +#define HW_ATL_TDM_DESCDLEN_WIDTH 10 /* default value of bitfield desc{d}_len[9:0] */ -#define tdm_descdlen_default 0x0 +#define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 /* tx int_desc_wrb_en bitfield definitions * preprocessor definitions for the bitfield "int_desc_wrb_en". @@ -1465,17 +1472,17 @@ */ /* register address for bitfield int_desc_wrb_en */ -#define tdm_int_desc_wrb_en_adr 0x00007b40 +#define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 /* bitmask for bitfield int_desc_wrb_en */ -#define tdm_int_desc_wrb_en_msk 0x00000002 +#define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 /* inverted bitmask for bitfield int_desc_wrb_en */ -#define tdm_int_desc_wrb_en_mskn 0xfffffffd +#define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd /* lower bit position of bitfield int_desc_wrb_en */ -#define tdm_int_desc_wrb_en_shift 1 +#define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 /* width of bitfield int_desc_wrb_en */ -#define tdm_int_desc_wrb_en_width 1 +#define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 /* default value of bitfield int_desc_wrb_en */ -#define tdm_int_desc_wrb_en_default 0x0 +#define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". @@ -1484,17 +1491,18 @@ */ /* register address for bitfield desc{d}_wrb_thresh[6:0] */ -#define tdm_descdwrb_thresh_adr(descriptor) (0x00007c18 + (descriptor) * 0x40) +#define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ + (0x00007c18 + (descriptor) * 0x40) /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ -#define tdm_descdwrb_thresh_msk 0x00007f00 +#define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ -#define tdm_descdwrb_thresh_mskn 0xffff80ff +#define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ -#define tdm_descdwrb_thresh_shift 8 +#define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 /* width of bitfield desc{d}_wrb_thresh[6:0] */ -#define tdm_descdwrb_thresh_width 7 +#define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ -#define tdm_descdwrb_thresh_default 0x0 +#define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 /* tx lso_tcp_flag_first[b:0] bitfield definitions * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". @@ -1502,17 +1510,17 @@ */ /* register address for bitfield lso_tcp_flag_first[b:0] */ -#define thm_lso_tcp_flag_first_adr 0x00007820 +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ -#define thm_lso_tcp_flag_first_msk 0x00000fff +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ -#define thm_lso_tcp_flag_first_mskn 0xfffff000 +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ -#define thm_lso_tcp_flag_first_shift 0 +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 /* width of bitfield lso_tcp_flag_first[b:0] */ -#define thm_lso_tcp_flag_first_width 12 +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 /* default value of bitfield lso_tcp_flag_first[b:0] */ -#define thm_lso_tcp_flag_first_default 0x0 +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 /* tx lso_tcp_flag_last[b:0] bitfield definitions * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". @@ -1520,17 +1528,17 @@ */ /* register address for bitfield lso_tcp_flag_last[b:0] */ -#define thm_lso_tcp_flag_last_adr 0x00007824 +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ -#define thm_lso_tcp_flag_last_msk 0x00000fff +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ -#define thm_lso_tcp_flag_last_mskn 0xfffff000 +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ -#define thm_lso_tcp_flag_last_shift 0 +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 /* width of bitfield lso_tcp_flag_last[b:0] */ -#define thm_lso_tcp_flag_last_width 12 +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 /* default value of bitfield lso_tcp_flag_last[b:0] */ -#define thm_lso_tcp_flag_last_default 0x0 +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 /* tx lso_tcp_flag_mid[b:0] bitfield definitions * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". @@ -1538,17 +1546,17 @@ */ /* Register address for bitfield lro_rsc_max[1F:0] */ -#define rpo_lro_rsc_max_adr 0x00005598 +#define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 /* Bitmask for bitfield lro_rsc_max[1F:0] */ -#define rpo_lro_rsc_max_msk 0xFFFFFFFF +#define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ -#define rpo_lro_rsc_max_mskn 0x00000000 +#define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ -#define rpo_lro_rsc_max_shift 0 +#define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 /* Width of bitfield lro_rsc_max[1F:0] */ -#define rpo_lro_rsc_max_width 32 +#define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 /* Default value of bitfield lro_rsc_max[1F:0] */ -#define rpo_lro_rsc_max_default 0x0 +#define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 /* RX lro_en[1F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_en[1F:0]". @@ -1556,17 +1564,17 @@ */ /* Register address for bitfield lro_en[1F:0] */ -#define rpo_lro_en_adr 0x00005590 +#define HW_ATL_RPO_LRO_EN_ADR 0x00005590 /* Bitmask for bitfield lro_en[1F:0] */ -#define rpo_lro_en_msk 0xFFFFFFFF +#define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF /* Inverted bitmask for bitfield lro_en[1F:0] */ -#define rpo_lro_en_mskn 0x00000000 +#define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 /* Lower bit position of bitfield lro_en[1F:0] */ -#define rpo_lro_en_shift 0 +#define HW_ATL_RPO_LRO_EN_SHIFT 0 /* Width of bitfield lro_en[1F:0] */ -#define rpo_lro_en_width 32 +#define HW_ATL_RPO_LRO_EN_WIDTH 32 /* Default value of bitfield lro_en[1F:0] */ -#define rpo_lro_en_default 0x0 +#define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 /* RX lro_ptopt_en Bitfield Definitions * Preprocessor definitions for the bitfield "lro_ptopt_en". @@ -1574,17 +1582,17 @@ */ /* Register address for bitfield lro_ptopt_en */ -#define rpo_lro_ptopt_en_adr 0x00005594 +#define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 /* Bitmask for bitfield lro_ptopt_en */ -#define rpo_lro_ptopt_en_msk 0x00008000 +#define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 /* Inverted bitmask for bitfield lro_ptopt_en */ -#define rpo_lro_ptopt_en_mskn 0xFFFF7FFF +#define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF /* Lower bit position of bitfield lro_ptopt_en */ -#define rpo_lro_ptopt_en_shift 15 +#define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 /* Width of bitfield lro_ptopt_en */ -#define rpo_lro_ptopt_en_width 1 +#define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 /* Default value of bitfield lro_ptopt_en */ -#define rpo_lro_ptopt_en_defalt 0x1 +#define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 /* RX lro_q_ses_lmt Bitfield Definitions * Preprocessor definitions for the bitfield "lro_q_ses_lmt". @@ -1592,17 +1600,17 @@ */ /* Register address for bitfield lro_q_ses_lmt */ -#define rpo_lro_qses_lmt_adr 0x00005594 +#define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 /* Bitmask for bitfield lro_q_ses_lmt */ -#define rpo_lro_qses_lmt_msk 0x00003000 +#define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 /* Inverted bitmask for bitfield lro_q_ses_lmt */ -#define rpo_lro_qses_lmt_mskn 0xFFFFCFFF +#define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF /* Lower bit position of bitfield lro_q_ses_lmt */ -#define rpo_lro_qses_lmt_shift 12 +#define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 /* Width of bitfield lro_q_ses_lmt */ -#define rpo_lro_qses_lmt_width 2 +#define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 /* Default value of bitfield lro_q_ses_lmt */ -#define rpo_lro_qses_lmt_default 0x1 +#define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". @@ -1610,17 +1618,17 @@ */ /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ -#define rpo_lro_tot_dsc_lmt_adr 0x00005594 +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ -#define rpo_lro_tot_dsc_lmt_msk 0x00000060 +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ -#define rpo_lro_tot_dsc_lmt_mskn 0xFFFFFF9F +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ -#define rpo_lro_tot_dsc_lmt_shift 5 +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ -#define rpo_lro_tot_dsc_lmt_width 2 +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ -#define rpo_lro_tot_dsc_lmt_defalt 0x1 +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 /* RX lro_pkt_min[4:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". @@ -1628,22 +1636,22 @@ */ /* Register address for bitfield lro_pkt_min[4:0] */ -#define rpo_lro_pkt_min_adr 0x00005594 +#define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 /* Bitmask for bitfield lro_pkt_min[4:0] */ -#define rpo_lro_pkt_min_msk 0x0000001F +#define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ -#define rpo_lro_pkt_min_mskn 0xFFFFFFE0 +#define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 /* Lower bit position of bitfield lro_pkt_min[4:0] */ -#define rpo_lro_pkt_min_shift 0 +#define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 /* Width of bitfield lro_pkt_min[4:0] */ -#define rpo_lro_pkt_min_width 5 +#define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 /* Default value of bitfield lro_pkt_min[4:0] */ -#define rpo_lro_pkt_min_default 0x8 +#define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 /* Width of bitfield lro{L}_des_max[1:0] */ -#define rpo_lro_ldes_max_width 2 +#define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 /* Default value of bitfield lro{L}_des_max[1:0] */ -#define rpo_lro_ldes_max_default 0x0 +#define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 /* RX lro_tb_div[11:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". @@ -1651,17 +1659,17 @@ */ /* Register address for bitfield lro_tb_div[11:0] */ -#define rpo_lro_tb_div_adr 0x00005620 +#define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 /* Bitmask for bitfield lro_tb_div[11:0] */ -#define rpo_lro_tb_div_msk 0xFFF00000 +#define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ -#define rpo_lro_tb_div_mskn 0x000FFFFF +#define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF /* Lower bit position of bitfield lro_tb_div[11:0] */ -#define rpo_lro_tb_div_shift 20 +#define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 /* Width of bitfield lro_tb_div[11:0] */ -#define rpo_lro_tb_div_width 12 +#define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 /* Default value of bitfield lro_tb_div[11:0] */ -#define rpo_lro_tb_div_default 0xC35 +#define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 /* RX lro_ina_ival[9:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". @@ -1669,17 +1677,17 @@ */ /* Register address for bitfield lro_ina_ival[9:0] */ -#define rpo_lro_ina_ival_adr 0x00005620 +#define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 /* Bitmask for bitfield lro_ina_ival[9:0] */ -#define rpo_lro_ina_ival_msk 0x000FFC00 +#define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ -#define rpo_lro_ina_ival_mskn 0xFFF003FF +#define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF /* Lower bit position of bitfield lro_ina_ival[9:0] */ -#define rpo_lro_ina_ival_shift 10 +#define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 /* Width of bitfield lro_ina_ival[9:0] */ -#define rpo_lro_ina_ival_width 10 +#define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 /* Default value of bitfield lro_ina_ival[9:0] */ -#define rpo_lro_ina_ival_default 0xA +#define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA /* RX lro_max_ival[9:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". @@ -1687,17 +1695,17 @@ */ /* Register address for bitfield lro_max_ival[9:0] */ -#define rpo_lro_max_ival_adr 0x00005620 +#define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 /* Bitmask for bitfield lro_max_ival[9:0] */ -#define rpo_lro_max_ival_msk 0x000003FF +#define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF /* Inverted bitmask for bitfield lro_max_ival[9:0] */ -#define rpo_lro_max_ival_mskn 0xFFFFFC00 +#define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 /* Lower bit position of bitfield lro_max_ival[9:0] */ -#define rpo_lro_max_ival_shift 0 +#define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 /* Width of bitfield lro_max_ival[9:0] */ -#define rpo_lro_max_ival_width 10 +#define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 /* Default value of bitfield lro_max_ival[9:0] */ -#define rpo_lro_max_ival_default 0x19 +#define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 /* TX dca{D}_cpuid[7:0] Bitfield Definitions * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". @@ -1706,17 +1714,17 @@ */ /* Register address for bitfield dca{D}_cpuid[7:0] */ -#define tdm_dca_dcpuid_adr(dca) (0x00008400 + (dca) * 0x4) +#define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) /* Bitmask for bitfield dca{D}_cpuid[7:0] */ -#define tdm_dca_dcpuid_msk 0x000000FF +#define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ -#define tdm_dca_dcpuid_mskn 0xFFFFFF00 +#define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ -#define tdm_dca_dcpuid_shift 0 +#define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 /* Width of bitfield dca{D}_cpuid[7:0] */ -#define tdm_dca_dcpuid_width 8 +#define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 /* Default value of bitfield dca{D}_cpuid[7:0] */ -#define tdm_dca_dcpuid_default 0x0 +#define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 /* TX dca{D}_desc_en Bitfield Definitions * Preprocessor definitions for the bitfield "dca{D}_desc_en". @@ -1725,17 +1733,17 @@ */ /* Register address for bitfield dca{D}_desc_en */ -#define tdm_dca_ddesc_en_adr(dca) (0x00008400 + (dca) * 0x4) +#define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) /* Bitmask for bitfield dca{D}_desc_en */ -#define tdm_dca_ddesc_en_msk 0x80000000 +#define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 /* Inverted bitmask for bitfield dca{D}_desc_en */ -#define tdm_dca_ddesc_en_mskn 0x7FFFFFFF +#define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF /* Lower bit position of bitfield dca{D}_desc_en */ -#define tdm_dca_ddesc_en_shift 31 +#define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 /* Width of bitfield dca{D}_desc_en */ -#define tdm_dca_ddesc_en_width 1 +#define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 /* Default value of bitfield dca{D}_desc_en */ -#define tdm_dca_ddesc_en_default 0x0 +#define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 /* TX desc{D}_en Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_en". @@ -1744,17 +1752,17 @@ */ /* Register address for bitfield desc{D}_en */ -#define tdm_desc_den_adr(descriptor) (0x00007C08 + (descriptor) * 0x40) +#define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) /* Bitmask for bitfield desc{D}_en */ -#define tdm_desc_den_msk 0x80000000 +#define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 /* Inverted bitmask for bitfield desc{D}_en */ -#define tdm_desc_den_mskn 0x7FFFFFFF +#define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF /* Lower bit position of bitfield desc{D}_en */ -#define tdm_desc_den_shift 31 +#define HW_ATL_TDM_DESC_DEN_SHIFT 31 /* Width of bitfield desc{D}_en */ -#define tdm_desc_den_width 1 +#define HW_ATL_TDM_DESC_DEN_WIDTH 1 /* Default value of bitfield desc{D}_en */ -#define tdm_desc_den_default 0x0 +#define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 /* TX desc{D}_hd[C:0] Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". @@ -1763,15 +1771,15 @@ */ /* Register address for bitfield desc{D}_hd[C:0] */ -#define tdm_desc_dhd_adr(descriptor) (0x00007C0C + (descriptor) * 0x40) +#define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) /* Bitmask for bitfield desc{D}_hd[C:0] */ -#define tdm_desc_dhd_msk 0x00001FFF +#define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ -#define tdm_desc_dhd_mskn 0xFFFFE000 +#define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 /* Lower bit position of bitfield desc{D}_hd[C:0] */ -#define tdm_desc_dhd_shift 0 +#define HW_ATL_TDM_DESC_DHD_SHIFT 0 /* Width of bitfield desc{D}_hd[C:0] */ -#define tdm_desc_dhd_width 13 +#define HW_ATL_TDM_DESC_DHD_WIDTH 13 /* TX desc{D}_len[9:0] Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". @@ -1780,17 +1788,17 @@ */ /* Register address for bitfield desc{D}_len[9:0] */ -#define tdm_desc_dlen_adr(descriptor) (0x00007C08 + (descriptor) * 0x40) +#define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) /* Bitmask for bitfield desc{D}_len[9:0] */ -#define tdm_desc_dlen_msk 0x00001FF8 +#define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ -#define tdm_desc_dlen_mskn 0xFFFFE007 +#define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 /* Lower bit position of bitfield desc{D}_len[9:0] */ -#define tdm_desc_dlen_shift 3 +#define HW_ATL_TDM_DESC_DLEN_SHIFT 3 /* Width of bitfield desc{D}_len[9:0] */ -#define tdm_desc_dlen_width 10 +#define HW_ATL_TDM_DESC_DLEN_WIDTH 10 /* Default value of bitfield desc{D}_len[9:0] */ -#define tdm_desc_dlen_default 0x0 +#define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". @@ -1799,18 +1807,18 @@ */ /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ -#define tdm_desc_dwrb_thresh_adr(descriptor) \ +#define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ (0x00007C18 + (descriptor) * 0x40) /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ -#define tdm_desc_dwrb_thresh_msk 0x00007F00 +#define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ -#define tdm_desc_dwrb_thresh_mskn 0xFFFF80FF +#define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ -#define tdm_desc_dwrb_thresh_shift 8 +#define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ -#define tdm_desc_dwrb_thresh_width 7 +#define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ -#define tdm_desc_dwrb_thresh_default 0x0 +#define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 /* TX tdm_int_mod_en Bitfield Definitions * Preprocessor definitions for the bitfield "tdm_int_mod_en". @@ -1818,34 +1826,34 @@ */ /* Register address for bitfield tdm_int_mod_en */ -#define tdm_int_mod_en_adr 0x00007B40 +#define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 /* Bitmask for bitfield tdm_int_mod_en */ -#define tdm_int_mod_en_msk 0x00000010 +#define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 /* Inverted bitmask for bitfield tdm_int_mod_en */ -#define tdm_int_mod_en_mskn 0xFFFFFFEF +#define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF /* Lower bit position of bitfield tdm_int_mod_en */ -#define tdm_int_mod_en_shift 4 +#define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 /* Width of bitfield tdm_int_mod_en */ -#define tdm_int_mod_en_width 1 +#define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 /* Default value of bitfield tdm_int_mod_en */ -#define tdm_int_mod_en_default 0x0 +#define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" */ /* register address for bitfield lso_tcp_flag_mid[b:0] */ -#define thm_lso_tcp_flag_mid_adr 0x00007820 +#define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ -#define thm_lso_tcp_flag_mid_msk 0x0fff0000 +#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ -#define thm_lso_tcp_flag_mid_mskn 0xf000ffff +#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ -#define thm_lso_tcp_flag_mid_shift 16 +#define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 /* width of bitfield lso_tcp_flag_mid[b:0] */ -#define thm_lso_tcp_flag_mid_width 12 +#define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 /* default value of bitfield lso_tcp_flag_mid[b:0] */ -#define thm_lso_tcp_flag_mid_default 0x0 +#define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 /* tx tx_buf_en bitfield definitions * preprocessor definitions for the bitfield "tx_buf_en". @@ -1853,17 +1861,17 @@ */ /* register address for bitfield tx_buf_en */ -#define tpb_tx_buf_en_adr 0x00007900 +#define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 /* bitmask for bitfield tx_buf_en */ -#define tpb_tx_buf_en_msk 0x00000001 +#define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 /* inverted bitmask for bitfield tx_buf_en */ -#define tpb_tx_buf_en_mskn 0xfffffffe +#define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe /* lower bit position of bitfield tx_buf_en */ -#define tpb_tx_buf_en_shift 0 +#define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 /* width of bitfield tx_buf_en */ -#define tpb_tx_buf_en_width 1 +#define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 /* default value of bitfield tx_buf_en */ -#define tpb_tx_buf_en_default 0x0 +#define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 /* tx tx{b}_hi_thresh[c:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". @@ -1872,17 +1880,17 @@ */ /* register address for bitfield tx{b}_hi_thresh[c:0] */ -#define tpb_txbhi_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10) +#define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ -#define tpb_txbhi_thresh_msk 0x1fff0000 +#define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ -#define tpb_txbhi_thresh_mskn 0xe000ffff +#define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ -#define tpb_txbhi_thresh_shift 16 +#define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 /* width of bitfield tx{b}_hi_thresh[c:0] */ -#define tpb_txbhi_thresh_width 13 +#define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 /* default value of bitfield tx{b}_hi_thresh[c:0] */ -#define tpb_txbhi_thresh_default 0x0 +#define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 /* tx tx{b}_lo_thresh[c:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". @@ -1891,17 +1899,17 @@ */ /* register address for bitfield tx{b}_lo_thresh[c:0] */ -#define tpb_txblo_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10) +#define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ -#define tpb_txblo_thresh_msk 0x00001fff +#define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ -#define tpb_txblo_thresh_mskn 0xffffe000 +#define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ -#define tpb_txblo_thresh_shift 0 +#define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 /* width of bitfield tx{b}_lo_thresh[c:0] */ -#define tpb_txblo_thresh_width 13 +#define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 /* default value of bitfield tx{b}_lo_thresh[c:0] */ -#define tpb_txblo_thresh_default 0x0 +#define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 /* tx dma_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "dma_sys_loopback". @@ -1909,17 +1917,17 @@ */ /* register address for bitfield dma_sys_loopback */ -#define tpb_dma_sys_lbk_adr 0x00007000 +#define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 /* bitmask for bitfield dma_sys_loopback */ -#define tpb_dma_sys_lbk_msk 0x00000040 +#define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 /* inverted bitmask for bitfield dma_sys_loopback */ -#define tpb_dma_sys_lbk_mskn 0xffffffbf +#define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf /* lower bit position of bitfield dma_sys_loopback */ -#define tpb_dma_sys_lbk_shift 6 +#define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 /* width of bitfield dma_sys_loopback */ -#define tpb_dma_sys_lbk_width 1 +#define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 /* default value of bitfield dma_sys_loopback */ -#define tpb_dma_sys_lbk_default 0x0 +#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 /* tx tx{b}_buf_size[7:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". @@ -1928,17 +1936,17 @@ */ /* register address for bitfield tx{b}_buf_size[7:0] */ -#define tpb_txbbuf_size_adr(buffer) (0x00007910 + (buffer) * 0x10) +#define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) /* bitmask for bitfield tx{b}_buf_size[7:0] */ -#define tpb_txbbuf_size_msk 0x000000ff +#define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ -#define tpb_txbbuf_size_mskn 0xffffff00 +#define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ -#define tpb_txbbuf_size_shift 0 +#define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 /* width of bitfield tx{b}_buf_size[7:0] */ -#define tpb_txbbuf_size_width 8 +#define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 /* default value of bitfield tx{b}_buf_size[7:0] */ -#define tpb_txbbuf_size_default 0x0 +#define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 /* tx tx_scp_ins_en bitfield definitions * preprocessor definitions for the bitfield "tx_scp_ins_en". @@ -1946,17 +1954,17 @@ */ /* register address for bitfield tx_scp_ins_en */ -#define tpb_tx_scp_ins_en_adr 0x00007900 +#define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 /* bitmask for bitfield tx_scp_ins_en */ -#define tpb_tx_scp_ins_en_msk 0x00000004 +#define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 /* inverted bitmask for bitfield tx_scp_ins_en */ -#define tpb_tx_scp_ins_en_mskn 0xfffffffb +#define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb /* lower bit position of bitfield tx_scp_ins_en */ -#define tpb_tx_scp_ins_en_shift 2 +#define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 /* width of bitfield tx_scp_ins_en */ -#define tpb_tx_scp_ins_en_width 1 +#define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 /* default value of bitfield tx_scp_ins_en */ -#define tpb_tx_scp_ins_en_default 0x0 +#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 /* tx ipv4_chk_en bitfield definitions * preprocessor definitions for the bitfield "ipv4_chk_en". @@ -1964,17 +1972,17 @@ */ /* register address for bitfield ipv4_chk_en */ -#define tpo_ipv4chk_en_adr 0x00007800 +#define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 /* bitmask for bitfield ipv4_chk_en */ -#define tpo_ipv4chk_en_msk 0x00000002 +#define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 /* inverted bitmask for bitfield ipv4_chk_en */ -#define tpo_ipv4chk_en_mskn 0xfffffffd +#define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd /* lower bit position of bitfield ipv4_chk_en */ -#define tpo_ipv4chk_en_shift 1 +#define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 /* width of bitfield ipv4_chk_en */ -#define tpo_ipv4chk_en_width 1 +#define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 /* default value of bitfield ipv4_chk_en */ -#define tpo_ipv4chk_en_default 0x0 +#define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 /* tx l4_chk_en bitfield definitions * preprocessor definitions for the bitfield "l4_chk_en". @@ -1982,17 +1990,17 @@ */ /* register address for bitfield l4_chk_en */ -#define tpol4chk_en_adr 0x00007800 +#define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 /* bitmask for bitfield l4_chk_en */ -#define tpol4chk_en_msk 0x00000001 +#define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 /* inverted bitmask for bitfield l4_chk_en */ -#define tpol4chk_en_mskn 0xfffffffe +#define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe /* lower bit position of bitfield l4_chk_en */ -#define tpol4chk_en_shift 0 +#define HW_ATL_TPOL4CHK_EN_SHIFT 0 /* width of bitfield l4_chk_en */ -#define tpol4chk_en_width 1 +#define HW_ATL_TPOL4CHK_EN_WIDTH 1 /* default value of bitfield l4_chk_en */ -#define tpol4chk_en_default 0x0 +#define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 /* tx pkt_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "pkt_sys_loopback". @@ -2000,17 +2008,17 @@ */ /* register address for bitfield pkt_sys_loopback */ -#define tpo_pkt_sys_lbk_adr 0x00007000 +#define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 /* bitmask for bitfield pkt_sys_loopback */ -#define tpo_pkt_sys_lbk_msk 0x00000080 +#define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 /* inverted bitmask for bitfield pkt_sys_loopback */ -#define tpo_pkt_sys_lbk_mskn 0xffffff7f +#define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f /* lower bit position of bitfield pkt_sys_loopback */ -#define tpo_pkt_sys_lbk_shift 7 +#define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 /* width of bitfield pkt_sys_loopback */ -#define tpo_pkt_sys_lbk_width 1 +#define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 /* default value of bitfield pkt_sys_loopback */ -#define tpo_pkt_sys_lbk_default 0x0 +#define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 /* tx data_tc_arb_mode bitfield definitions * preprocessor definitions for the bitfield "data_tc_arb_mode". @@ -2018,17 +2026,17 @@ */ /* register address for bitfield data_tc_arb_mode */ -#define tps_data_tc_arb_mode_adr 0x00007100 +#define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 /* bitmask for bitfield data_tc_arb_mode */ -#define tps_data_tc_arb_mode_msk 0x00000001 +#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 /* inverted bitmask for bitfield data_tc_arb_mode */ -#define tps_data_tc_arb_mode_mskn 0xfffffffe +#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe /* lower bit position of bitfield data_tc_arb_mode */ -#define tps_data_tc_arb_mode_shift 0 +#define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 /* width of bitfield data_tc_arb_mode */ -#define tps_data_tc_arb_mode_width 1 +#define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 /* default value of bitfield data_tc_arb_mode */ -#define tps_data_tc_arb_mode_default 0x0 +#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 /* tx desc_rate_ta_rst bitfield definitions * preprocessor definitions for the bitfield "desc_rate_ta_rst". @@ -2036,17 +2044,17 @@ */ /* register address for bitfield desc_rate_ta_rst */ -#define tps_desc_rate_ta_rst_adr 0x00007310 +#define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 /* bitmask for bitfield desc_rate_ta_rst */ -#define tps_desc_rate_ta_rst_msk 0x80000000 +#define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 /* inverted bitmask for bitfield desc_rate_ta_rst */ -#define tps_desc_rate_ta_rst_mskn 0x7fffffff +#define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff /* lower bit position of bitfield desc_rate_ta_rst */ -#define tps_desc_rate_ta_rst_shift 31 +#define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 /* width of bitfield desc_rate_ta_rst */ -#define tps_desc_rate_ta_rst_width 1 +#define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 /* default value of bitfield desc_rate_ta_rst */ -#define tps_desc_rate_ta_rst_default 0x0 +#define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 /* tx desc_rate_limit[a:0] bitfield definitions * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". @@ -2054,17 +2062,17 @@ */ /* register address for bitfield desc_rate_limit[a:0] */ -#define tps_desc_rate_lim_adr 0x00007310 +#define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 /* bitmask for bitfield desc_rate_limit[a:0] */ -#define tps_desc_rate_lim_msk 0x000007ff +#define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff /* inverted bitmask for bitfield desc_rate_limit[a:0] */ -#define tps_desc_rate_lim_mskn 0xfffff800 +#define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 /* lower bit position of bitfield desc_rate_limit[a:0] */ -#define tps_desc_rate_lim_shift 0 +#define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 /* width of bitfield desc_rate_limit[a:0] */ -#define tps_desc_rate_lim_width 11 +#define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 /* default value of bitfield desc_rate_limit[a:0] */ -#define tps_desc_rate_lim_default 0x0 +#define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 /* tx desc_tc_arb_mode[1:0] bitfield definitions * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". @@ -2072,17 +2080,17 @@ */ /* register address for bitfield desc_tc_arb_mode[1:0] */ -#define tps_desc_tc_arb_mode_adr 0x00007200 +#define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ -#define tps_desc_tc_arb_mode_msk 0x00000003 +#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ -#define tps_desc_tc_arb_mode_mskn 0xfffffffc +#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ -#define tps_desc_tc_arb_mode_shift 0 +#define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 /* width of bitfield desc_tc_arb_mode[1:0] */ -#define tps_desc_tc_arb_mode_width 2 +#define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 /* default value of bitfield desc_tc_arb_mode[1:0] */ -#define tps_desc_tc_arb_mode_default 0x0 +#define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". @@ -2091,17 +2099,17 @@ */ /* register address for bitfield desc_tc{t}_credit_max[b:0] */ -#define tps_desc_tctcredit_max_adr(tc) (0x00007210 + (tc) * 0x4) +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ -#define tps_desc_tctcredit_max_msk 0x0fff0000 +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ -#define tps_desc_tctcredit_max_mskn 0xf000ffff +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ -#define tps_desc_tctcredit_max_shift 16 +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 /* width of bitfield desc_tc{t}_credit_max[b:0] */ -#define tps_desc_tctcredit_max_width 12 +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ -#define tps_desc_tctcredit_max_default 0x0 +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 /* tx desc_tc{t}_weight[8:0] bitfield definitions * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". @@ -2110,17 +2118,17 @@ */ /* register address for bitfield desc_tc{t}_weight[8:0] */ -#define tps_desc_tctweight_adr(tc) (0x00007210 + (tc) * 0x4) +#define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) /* bitmask for bitfield desc_tc{t}_weight[8:0] */ -#define tps_desc_tctweight_msk 0x000001ff +#define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ -#define tps_desc_tctweight_mskn 0xfffffe00 +#define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ -#define tps_desc_tctweight_shift 0 +#define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 /* width of bitfield desc_tc{t}_weight[8:0] */ -#define tps_desc_tctweight_width 9 +#define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 /* default value of bitfield desc_tc{t}_weight[8:0] */ -#define tps_desc_tctweight_default 0x0 +#define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 /* tx desc_vm_arb_mode bitfield definitions * preprocessor definitions for the bitfield "desc_vm_arb_mode". @@ -2128,17 +2136,17 @@ */ /* register address for bitfield desc_vm_arb_mode */ -#define tps_desc_vm_arb_mode_adr 0x00007300 +#define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 /* bitmask for bitfield desc_vm_arb_mode */ -#define tps_desc_vm_arb_mode_msk 0x00000001 +#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 /* inverted bitmask for bitfield desc_vm_arb_mode */ -#define tps_desc_vm_arb_mode_mskn 0xfffffffe +#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe /* lower bit position of bitfield desc_vm_arb_mode */ -#define tps_desc_vm_arb_mode_shift 0 +#define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 /* width of bitfield desc_vm_arb_mode */ -#define tps_desc_vm_arb_mode_width 1 +#define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 /* default value of bitfield desc_vm_arb_mode */ -#define tps_desc_vm_arb_mode_default 0x0 +#define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 /* tx data_tc{t}_credit_max[b:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". @@ -2147,17 +2155,17 @@ */ /* register address for bitfield data_tc{t}_credit_max[b:0] */ -#define tps_data_tctcredit_max_adr(tc) (0x00007110 + (tc) * 0x4) +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ -#define tps_data_tctcredit_max_msk 0x0fff0000 +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ -#define tps_data_tctcredit_max_mskn 0xf000ffff +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ -#define tps_data_tctcredit_max_shift 16 +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 /* width of bitfield data_tc{t}_credit_max[b:0] */ -#define tps_data_tctcredit_max_width 12 +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 /* default value of bitfield data_tc{t}_credit_max[b:0] */ -#define tps_data_tctcredit_max_default 0x0 +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 /* tx data_tc{t}_weight[8:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". @@ -2166,17 +2174,17 @@ */ /* register address for bitfield data_tc{t}_weight[8:0] */ -#define tps_data_tctweight_adr(tc) (0x00007110 + (tc) * 0x4) +#define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) /* bitmask for bitfield data_tc{t}_weight[8:0] */ -#define tps_data_tctweight_msk 0x000001ff +#define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ -#define tps_data_tctweight_mskn 0xfffffe00 +#define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ -#define tps_data_tctweight_shift 0 +#define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 /* width of bitfield data_tc{t}_weight[8:0] */ -#define tps_data_tctweight_width 9 +#define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 /* default value of bitfield data_tc{t}_weight[8:0] */ -#define tps_data_tctweight_default 0x0 +#define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 /* tx reg_res_dsbl bitfield definitions * preprocessor definitions for the bitfield "reg_res_dsbl". @@ -2184,17 +2192,17 @@ */ /* register address for bitfield reg_res_dsbl */ -#define tx_reg_res_dsbl_adr 0x00007000 +#define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 /* bitmask for bitfield reg_res_dsbl */ -#define tx_reg_res_dsbl_msk 0x20000000 +#define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 /* inverted bitmask for bitfield reg_res_dsbl */ -#define tx_reg_res_dsbl_mskn 0xdfffffff +#define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff /* lower bit position of bitfield reg_res_dsbl */ -#define tx_reg_res_dsbl_shift 29 +#define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 /* width of bitfield reg_res_dsbl */ -#define tx_reg_res_dsbl_width 1 +#define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 /* default value of bitfield reg_res_dsbl */ -#define tx_reg_res_dsbl_default 0x1 +#define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 /* mac_phy register access busy bitfield definitions * preprocessor definitions for the bitfield "register access busy". @@ -2202,15 +2210,15 @@ */ /* register address for bitfield register access busy */ -#define msm_reg_access_busy_adr 0x00004400 +#define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 /* bitmask for bitfield register access busy */ -#define msm_reg_access_busy_msk 0x00001000 +#define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 /* inverted bitmask for bitfield register access busy */ -#define msm_reg_access_busy_mskn 0xffffefff +#define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff /* lower bit position of bitfield register access busy */ -#define msm_reg_access_busy_shift 12 +#define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 /* width of bitfield register access busy */ -#define msm_reg_access_busy_width 1 +#define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 /* mac_phy msm register address[7:0] bitfield definitions * preprocessor definitions for the bitfield "msm register address[7:0]". @@ -2218,17 +2226,17 @@ */ /* register address for bitfield msm register address[7:0] */ -#define msm_reg_addr_adr 0x00004400 +#define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 /* bitmask for bitfield msm register address[7:0] */ -#define msm_reg_addr_msk 0x000000ff +#define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff /* inverted bitmask for bitfield msm register address[7:0] */ -#define msm_reg_addr_mskn 0xffffff00 +#define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 /* lower bit position of bitfield msm register address[7:0] */ -#define msm_reg_addr_shift 0 +#define HW_ATL_MSM_REG_ADDR_SHIFT 0 /* width of bitfield msm register address[7:0] */ -#define msm_reg_addr_width 8 +#define HW_ATL_MSM_REG_ADDR_WIDTH 8 /* default value of bitfield msm register address[7:0] */ -#define msm_reg_addr_default 0x0 +#define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 /* mac_phy register read strobe bitfield definitions * preprocessor definitions for the bitfield "register read strobe". @@ -2236,17 +2244,17 @@ */ /* register address for bitfield register read strobe */ -#define msm_reg_rd_strobe_adr 0x00004400 +#define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 /* bitmask for bitfield register read strobe */ -#define msm_reg_rd_strobe_msk 0x00000200 +#define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 /* inverted bitmask for bitfield register read strobe */ -#define msm_reg_rd_strobe_mskn 0xfffffdff +#define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff /* lower bit position of bitfield register read strobe */ -#define msm_reg_rd_strobe_shift 9 +#define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 /* width of bitfield register read strobe */ -#define msm_reg_rd_strobe_width 1 +#define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 /* default value of bitfield register read strobe */ -#define msm_reg_rd_strobe_default 0x0 +#define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 /* mac_phy msm register read data[31:0] bitfield definitions * preprocessor definitions for the bitfield "msm register read data[31:0]". @@ -2254,15 +2262,15 @@ */ /* register address for bitfield msm register read data[31:0] */ -#define msm_reg_rd_data_adr 0x00004408 +#define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 /* bitmask for bitfield msm register read data[31:0] */ -#define msm_reg_rd_data_msk 0xffffffff +#define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff /* inverted bitmask for bitfield msm register read data[31:0] */ -#define msm_reg_rd_data_mskn 0x00000000 +#define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 /* lower bit position of bitfield msm register read data[31:0] */ -#define msm_reg_rd_data_shift 0 +#define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 /* width of bitfield msm register read data[31:0] */ -#define msm_reg_rd_data_width 32 +#define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 /* mac_phy msm register write data[31:0] bitfield definitions * preprocessor definitions for the bitfield "msm register write data[31:0]". @@ -2270,17 +2278,17 @@ */ /* register address for bitfield msm register write data[31:0] */ -#define msm_reg_wr_data_adr 0x00004404 +#define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 /* bitmask for bitfield msm register write data[31:0] */ -#define msm_reg_wr_data_msk 0xffffffff +#define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff /* inverted bitmask for bitfield msm register write data[31:0] */ -#define msm_reg_wr_data_mskn 0x00000000 +#define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 /* lower bit position of bitfield msm register write data[31:0] */ -#define msm_reg_wr_data_shift 0 +#define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 /* width of bitfield msm register write data[31:0] */ -#define msm_reg_wr_data_width 32 +#define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 /* default value of bitfield msm register write data[31:0] */ -#define msm_reg_wr_data_default 0x0 +#define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 /* mac_phy register write strobe bitfield definitions * preprocessor definitions for the bitfield "register write strobe". @@ -2288,17 +2296,17 @@ */ /* register address for bitfield register write strobe */ -#define msm_reg_wr_strobe_adr 0x00004400 +#define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 /* bitmask for bitfield register write strobe */ -#define msm_reg_wr_strobe_msk 0x00000100 +#define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 /* inverted bitmask for bitfield register write strobe */ -#define msm_reg_wr_strobe_mskn 0xfffffeff +#define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff /* lower bit position of bitfield register write strobe */ -#define msm_reg_wr_strobe_shift 8 +#define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 /* width of bitfield register write strobe */ -#define msm_reg_wr_strobe_width 1 +#define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 /* default value of bitfield register write strobe */ -#define msm_reg_wr_strobe_default 0x0 +#define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 /* mif soft reset bitfield definitions * preprocessor definitions for the bitfield "soft reset". @@ -2306,17 +2314,17 @@ */ /* register address for bitfield soft reset */ -#define glb_soft_res_adr 0x00000000 +#define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 /* bitmask for bitfield soft reset */ -#define glb_soft_res_msk 0x00008000 +#define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 /* inverted bitmask for bitfield soft reset */ -#define glb_soft_res_mskn 0xffff7fff +#define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff /* lower bit position of bitfield soft reset */ -#define glb_soft_res_shift 15 +#define HW_ATL_GLB_SOFT_RES_SHIFT 15 /* width of bitfield soft reset */ -#define glb_soft_res_width 1 +#define HW_ATL_GLB_SOFT_RES_WIDTH 1 /* default value of bitfield soft reset */ -#define glb_soft_res_default 0x0 +#define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 /* mif register reset disable bitfield definitions * preprocessor definitions for the bitfield "register reset disable". @@ -2324,27 +2332,27 @@ */ /* register address for bitfield register reset disable */ -#define glb_reg_res_dis_adr 0x00000000 +#define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 /* bitmask for bitfield register reset disable */ -#define glb_reg_res_dis_msk 0x00004000 +#define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 /* inverted bitmask for bitfield register reset disable */ -#define glb_reg_res_dis_mskn 0xffffbfff +#define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff /* lower bit position of bitfield register reset disable */ -#define glb_reg_res_dis_shift 14 +#define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 /* width of bitfield register reset disable */ -#define glb_reg_res_dis_width 1 +#define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 /* default value of bitfield register reset disable */ -#define glb_reg_res_dis_default 0x1 +#define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 /* tx dma debug control definitions */ -#define tx_dma_debug_ctl_adr 0x00008920u +#define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u /* tx dma descriptor base address msw definitions */ -#define tx_dma_desc_base_addrmsw_adr(descriptor) \ +#define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ (0x00007c04u + (descriptor) * 0x40) /* tx dma total request limit */ -#define tx_dma_total_req_limit_adr 0x00007b20u +#define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u /* tx interrupt moderation control register definitions * Preprocessor definitions for TX Interrupt Moderation Control Register @@ -2352,7 +2360,7 @@ * Parameter: queue {Q} | stride size 0x4 | range [0, 31] */ -#define tx_intr_moderation_ctl_adr(queue) (0x00008980u + (queue) * 0x4) +#define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) /* pcie reg_res_dsbl bitfield definitions * preprocessor definitions for the bitfield "reg_res_dsbl". @@ -2360,22 +2368,23 @@ */ /* register address for bitfield reg_res_dsbl */ -#define pci_reg_res_dsbl_adr 0x00001000 +#define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 /* bitmask for bitfield reg_res_dsbl */ -#define pci_reg_res_dsbl_msk 0x20000000 +#define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 /* inverted bitmask for bitfield reg_res_dsbl */ -#define pci_reg_res_dsbl_mskn 0xdfffffff +#define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff /* lower bit position of bitfield reg_res_dsbl */ -#define pci_reg_res_dsbl_shift 29 +#define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 /* width of bitfield reg_res_dsbl */ -#define pci_reg_res_dsbl_width 1 +#define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 /* default value of bitfield reg_res_dsbl */ -#define pci_reg_res_dsbl_default 0x1 +#define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 /* PCI core control register */ -#define pci_reg_control6_adr 0x1014u +#define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u /* global microprocessor scratch pad definitions */ -#define glb_cpu_scratch_scp_adr(scratch_scp) (0x00000300u + (scratch_scp) * 0x4) +#define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ + (0x00000300u + (scratch_scp) * 0x4) #endif /* HW_ATL_LLH_INTERNAL_H */

[08/28] net: aquantia: Fix register definitions to linux style

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