From patchwork Fri Feb 24 15:58:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seth Forshee X-Patchwork-Id: 732182 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) by ozlabs.org (Postfix) with ESMTP id 3vVG442H3hz9ryk; Sat, 25 Feb 2017 02:58:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=canonical-com.20150623.gappssmtp.com header.i=@canonical-com.20150623.gappssmtp.com header.b="dGAKS2Uf"; dkim-atps=neutral Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1chIGW-0002XG-P6; Fri, 24 Feb 2017 15:58:40 +0000 Received: from mail-it0-f49.google.com ([209.85.214.49]) by huckleberry.canonical.com with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.76) (envelope-from ) id 1chIGG-0002SA-37 for kernel-team@lists.ubuntu.com; Fri, 24 Feb 2017 15:58:24 +0000 Received: by mail-it0-f49.google.com with SMTP id d9so12561964itc.0 for ; Fri, 24 Feb 2017 07:58:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=xnONZS/nJsVJiWpg+UNych8SS4uLvn0HVWeexMqTzpc=; b=dGAKS2Uf1DIS+B6PZnmR8dPcYnT1pyhVYzkiMILeNRiyOuFVLNFLMR9GlY4sGjG4ZQ kbFWwpnjpV19etB/qjy59Ez0gjYaSEvTuxaLKMDYgOdL7pe176IfprygfzYdI/KGS5TS 532FnOAf6QB6OrEAKt6HpiJcQdGaux4Z6ikVVYnjg3kOdXLDVbZsf4WaqFYn0e/Lu/mX FMOAz7ghLi4FU6qt7ifLbMgh+Ak0Bzv/dRlDILUrVR3oHaihzA2ptwSEocm6UVjKElhD dqqp2DcpAZlsGHSEenLpIg4HEbiu5v88EC77kf4C/gPTNlvMRcDlkV2Miirx6imcS22Y fNXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=xnONZS/nJsVJiWpg+UNych8SS4uLvn0HVWeexMqTzpc=; b=Pxibror/cV/S1Fg5A0+zJV2zmDcodemI49jL1LHPxXDMpwjpP1SrIrmyY0MS2XfkM7 nkxcZ2uO1wfVD6+2bOYrUnXe/sJ6bJ6tn47m5QvH+3bFqkcYVv/xQMLfb4d3WCGeX+Bt Pu0/Lz99gnAy6ygcddEML/gJAY3ggUhKoaF/n+QDM6L8qKh3pcOCdqweTb/vcYOVB1wn VYmuNfzpO2HWe1ip1Dea+1Quh9UrqUbkqHHyqPzYLB8r3iIfNfISEgmm7adRVZDwN3Ta rMtDGn+R61cffNeaG2FD1Pk332rK0h96tEl5wXIjjEkKoXZq/mb4AlzgvQ7l/30Nn2Ak H+7w== X-Gm-Message-State: AMke39m2Kj2W1nK5byWqQDyQOjcESWOQjFp0eto6LcP+iDBnqMSEOfKlk6sqCCDhDrMBY1dI X-Received: by 10.107.147.87 with SMTP id v84mr2940757iod.63.1487951902607; Fri, 24 Feb 2017 07:58:22 -0800 (PST) Received: from localhost ([2605:a601:aa7:8220:d525:2d8c:d0b4:d509]) by smtp.gmail.com with ESMTPSA id 202sm850638ity.8.2017.02.24.07.58.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Feb 2017 07:58:22 -0800 (PST) From: Seth Forshee To: kernel-team@lists.ubuntu.com Subject: [PATCH 2/5][Yakkety SRU] powerpc/mm/radix: Update pte update sequence for pte clear case Date: Fri, 24 Feb 2017 09:58:16 -0600 Message-Id: <1487951899-94245-3-git-send-email-seth.forshee@canonical.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487951899-94245-1-git-send-email-seth.forshee@canonical.com> References: <1487951899-94245-1-git-send-email-seth.forshee@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.14 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: kernel-team-bounces@lists.ubuntu.com From: "Aneesh Kumar K.V" BugLink: http://bugs.launchpad.net/bugs/1667116 In the kernel we do follow the below sequence in different code paths. pte = ptep_get_clear(ptep) .... set_pte_at(ptep, pte) We do that for mremap, autonuma protection update and softdirty clearing. This implies our optimization to skip a tlb flush when clearing a pte update is not valid, because for DD1 system that followup set_pte_at will be done witout doing the required tlbflush. Fix that by always doing the dd1 style pte update irrespective of new_pte value. In a later patch we will optimize the application exit case. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Aneesh Kumar K.V Tested-by: Michael Neuling Signed-off-by: Michael Ellerman (cherry picked from linux-next commit ca94573b9c69d224e50e1084a2776772f4ea030d) Signed-off-by: Seth Forshee --- arch/powerpc/include/asm/book3s/64/radix.h | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h index b4d1302387a3..70a3cdcdbe47 100644 --- a/arch/powerpc/include/asm/book3s/64/radix.h +++ b/arch/powerpc/include/asm/book3s/64/radix.h @@ -144,16 +144,10 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm, * new value of pte */ new_pte = (old_pte | set) & ~clr; - /* - * If we are trying to clear the pte, we can skip - * the below sequence and batch the tlb flush. The - * tlb flush batching is done by mmu gather code - */ - if (new_pte) { - asm volatile("ptesync" : : : "memory"); - radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); + asm volatile("ptesync" : : : "memory"); + radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); + if (new_pte) __radix_pte_update(ptep, 0, new_pte); - } } else old_pte = __radix_pte_update(ptep, clr, set); asm volatile("ptesync" : : : "memory");