From patchwork Wed Feb 17 13:44:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Ian King X-Patchwork-Id: 45632 X-Patchwork-Delegate: stefan.bader@canonical.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from chlorine.canonical.com (chlorine.canonical.com [91.189.94.204]) by ozlabs.org (Postfix) with ESMTP id DAC6CB7D83 for ; Thu, 18 Feb 2010 00:44:16 +1100 (EST) Received: from localhost ([127.0.0.1] helo=chlorine.canonical.com) by chlorine.canonical.com with esmtp (Exim 4.69) (envelope-from ) id 1NhkCK-0002MQ-Ke; Wed, 17 Feb 2010 13:44:12 +0000 Received: from adelie.canonical.com ([91.189.90.139]) by chlorine.canonical.com with esmtp (Exim 4.69) (envelope-from ) id 1NhkCI-0002LU-91 for kernel-team@lists.ubuntu.com; Wed, 17 Feb 2010 13:44:10 +0000 Received: from hutte.canonical.com ([91.189.90.181]) by adelie.canonical.com with esmtp (Exim 4.69 #1 (Debian)) id 1NhkCI-0000qs-7t for ; Wed, 17 Feb 2010 13:44:10 +0000 Received: from cpc2-craw3-0-0-cust718.croy.cable.virginmedia.com ([82.44.34.207] helo=localhost) by hutte.canonical.com with esmtpsa (TLS-1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.69) (envelope-from ) id 1NhkCI-000777-0V for kernel-team@lists.ubuntu.com; Wed, 17 Feb 2010 13:44:10 +0000 From: Colin King To: kernel-team@lists.ubuntu.com Subject: [PATCH 1/1] UBUNTU: x86: work around X86-32 kernel failures on Intel Atom CPU Date: Wed, 17 Feb 2010 13:44:08 +0000 Message-Id: <1266414248-25548-2-git-send-email-colin.king@canonical.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1266414248-25548-1-git-send-email-colin.king@canonical.com> References: <1266414248-25548-1-git-send-email-colin.king@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.9 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: kernel-team-bounces@lists.ubuntu.com Errors-To: kernel-team-bounces@lists.ubuntu.com From: Colin Ian King BugLink: https://bugs.launchpad.net/bugs/523112 This is a workaround to errata AAE44 as listed in http://download.intel.com/design/processor/specupdt/319536.pdf, page 33, namely: "Code Fetch May Occur to Incorrect Address After a Large Page is Split into 4-KB Byte Pages". This is the same as Errata AAH41 (Atom 3xx series) but named AAE44 for the Atom Z5xx series. This fix is not totally bullet proof. There is still a possibility of a race between __set_pmd_pte and __flush_tlb_all() during which the other hyperthread could do a code fetch and get garbage. Hence this patch narrows the window for the race but does not completely prevent it. This patch is a backport of the upstream commit 211b3d03c7400f48a781977a50104c9d12f4e229, the original commit message was as follows: Impact: work around boot crash Work around Intel Atom erratum AAH41 (probabilistically) - it's triggering in the field. Reported-by: Linus Torvalds Tested-by: Kyle McMartin Signed-off-by: Ingo Molnar Signed-off-by: Colin Ian King --- arch/x86/mm/pageattr_32.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/x86/mm/pageattr_32.c b/arch/x86/mm/pageattr_32.c index 260073c..92c91ea 100644 --- a/arch/x86/mm/pageattr_32.c +++ b/arch/x86/mm/pageattr_32.c @@ -65,6 +65,17 @@ static struct page *split_large_page(unsigned long address, pgprot_t prot, set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, addr == address ? prot : ref_prot)); } + + /* + * Intel Atom errata AAH41 and AAE44 workaround. + * + * The real fix should be in hw or in a microcode update, but + * we also probabilistically try to reduce the window of having + * a large TLB mixed with 4K TLBs while instruction fetches are + * going on. + */ + __flush_tlb_all(); + return base; }