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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id x28sm8178509pfj.73.2020.08.13.23.57.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:42 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 00/31][SRU][OEM-5.6] Add TGL+ SAGV display support Date: Fri, 14 Aug 2020 14:57:09 +0800 Message-Id: <20200814065740.276039-1-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.196; envelope-from=vicamo@gmail.com; helo=mail-pl1-f196.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1891451 [Impact] On platforms with UHD panel, massive drawing area updates may cause screen to flash as half-baked render buffers with black areas being renedered. [Fix] This turns out to be the lack of full support to Intel System Agent Geyserville (SAGV), which has been landed to kernel v5.8. The required fix resides in https://patchwork.freedesktop.org/series/75129/, which seems a rolling set that its early parts have been committed separatedly several times. This patchset also depends on https://patchwork.freedesktop.org/series/72301/, which attempts to make global state handling more standardized. [Test Case] 1. Trigger massive rect updates, e.g. cat a lengthy file in xterm, dump kernel git history, etc. 2. Observe if screen flashes with half black panes, sometimes black stripes, etc. [Regression Potential] Medium. This is to backport a new feature landed to kernel early this year, even there is no later fixes patch found so far, it could still introduce incompatibility to older kernels. So far it behaves on both UHD and other lower resolutions. Matt Roper (1): drm/i915/gen11: Add additional pcode status values Stanislav Lisovskiy (14): drm/i915: Start passing latency as parameter drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv drm/i915: Add pre/post plane updates for SAGV drm/i915: Add intel_atomic_get_bw_*_state helpers drm/i915: Use bw state for per crtc SAGV evaluation drm/i915: Track active_pipes in bw_state drm/i915: Rename bw_state to new_bw_state drm/i915: Introduce skl_plane_wm_level accessor. drm/i915: Extract skl SAGV checking drm/i915: Make active_pipes check skl specific drm/i915: Added required new PCode commands drm/i915: Add TGL+ SAGV support drm/i915: Restrict qgv points which don't have enough bandwidth. drm/i915: Enable SAGV support for Gen12 Ville Syrjälä (16): drm/i915: Move more cdclk state handling into the cdclk code drm/i915: Collect more cdclk state under the same roof drm/i915: s/need_cd2x_updare/can_cd2x_update/ drm/i915: s/cdclk_state/cdclk_config/ drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention drm/i915: Extract intel_cdclk_state drm/i915: swap() the entire cdclk state drm/i915: s/init_cdclk/init_cdclk_hw/ drm/i915: Move intel_atomic_state_free() into intel_atomic.c drm/i915: Introduce better global state handling drm/i915: Convert bandwidth state to global state drm/i915: Introduce intel_calc_active_pipes() drm/i915: Don't check uv_wm in skl_plane_wm_equals() drm/i915: Don't check for wm changes until we've compute the wms fully drm/i915: Enable transition watermarks for glk drm/i915: Implement display w/a 1140 for glk/cnl drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_atomic.c | 27 +- drivers/gpu/drm/i915/display/intel_atomic.h | 5 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +- drivers/gpu/drm/i915/display/intel_audio.c | 6 +- drivers/gpu/drm/i915/display/intel_bw.c | 213 ++++-- drivers/gpu/drm/i915/display/intel_bw.h | 31 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 630 +++++++++--------- drivers/gpu/drm/i915/display/intel_cdclk.h | 27 +- drivers/gpu/drm/i915/display/intel_display.c | 134 ++-- drivers/gpu/drm/i915/display/intel_display.h | 3 + .../drm/i915/display/intel_display_power.c | 24 +- .../drm/i915/display/intel_display_types.h | 32 +- .../gpu/drm/i915/display/intel_global_state.c | 223 +++++++ .../gpu/drm/i915/display/intel_global_state.h | 87 +++ drivers/gpu/drm/i915/i915_drv.h | 67 +- drivers/gpu/drm/i915/i915_reg.h | 6 + drivers/gpu/drm/i915/intel_pm.c | 379 +++++++++-- drivers/gpu/drm/i915/intel_pm.h | 6 +- drivers/gpu/drm/i915/intel_sideband.c | 6 + 20 files changed, 1326 insertions(+), 587 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h