From patchwork Wed Nov 27 08:00:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1201386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47NCrS19t5z9sSt; Wed, 27 Nov 2019 19:00:55 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1iZsFl-0000pb-9Y; Wed, 27 Nov 2019 08:00:49 +0000 Received: from mail-pj1-f68.google.com ([209.85.216.68]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1iZsFV-0000eg-Rk for kernel-team@lists.ubuntu.com; Wed, 27 Nov 2019 08:00:34 +0000 Received: by mail-pj1-f68.google.com with SMTP id gc1so9554350pjb.8 for ; Wed, 27 Nov 2019 00:00:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=Epwn5onLXbKVBoBY8rcOn0Axnv+WvRj4lqRPrMa7E0Q=; b=bo9TBg07rbBJBHLkOIEH5xZUa7W7VbZU5tcf+0pgW/ENDZFcsY02P713BMU4UPd6ou fmNj0CAarOdvQewEZ6OuipvgOgP8QFBN7i6bsgfWDW/W5RSwFT/W2mcMsFZNwI8U7QZu X5chPg6riIm4QA56uEP5hfawySvyeCgYUIn/GIAN3+KZh7adfe+3cOzoVUnEV+j7Uf6h uVTziQ4n39lRmXo4Fornpe3tEZ9qc+ZCVA88pT28wgqx1pN5DRABtknPhCZz+D+iQ6IB MfW/UdtdEoXWJ7id6ZubNpFQivK1WlaVtZyfRIuyTSP12Pyy0fXL95E9FfUI8gI1Ijpu qwbA== X-Gm-Message-State: APjAAAX5IVAjeCpG7GIJrJ6SQgbD76Y7f5YcMLzRhGzidytT7ZLRP/zW dqXUDek8elo7sMxnnRV8YwE+RGg8 X-Google-Smtp-Source: APXvYqzweLUNfvnd9epmiSbZknD1EeFdYQ8Oz5E3ndC/i1qU9x5PfzWi57E7hrV0w9YAzLyVlqt95g== X-Received: by 2002:a17:90a:ec13:: with SMTP id l19mr4619318pjy.0.1574841631087; Wed, 27 Nov 2019 00:00:31 -0800 (PST) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id 20sm14679245pgw.71.2019.11.27.00.00.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2019 00:00:30 -0800 (PST) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [SRU][D/OEM-OSP1-B][PATCH v2 00/20] Add perf support for Comet Lake/Ice Lake CPU Date: Wed, 27 Nov 2019 16:00:08 +0800 Message-Id: <20191127080028.200261-1-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1848978 [Impact] There is no complete perf support for Comet Lake CPU. For Ice Lake, some changes has been included in v5.3, but still misses CPU IDs. [Fix] perf support for Comet Lake is based on previous works for Ice Lake, so changes for both have to be backported. [Test Case] On platforms with Comet Lake/Ice Lake CPUs, one should find new cstate_pkg events c{8,9,10}-residency appear in output of `perf list` for use. [Regression Potential] Low. This backports perf support for previously incompletedly supported cpu models. V2: - add one more patch from commit 6b89d4c1ae85 ("perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking"). Andi Kleen (3): perf/x86/kvm: Avoid unnecessary work in guest filtering perf/x86/intel: Extract memory code PEBS parser for reuse perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them Kan Liang (14): x86/cpufeature: Add facility to check for min microcode revisions perf/x86: Support outputting XMM registers perf/x86/intel/ds: Extract code of event update in short period perf/x86/intel: Support adaptive PEBS v4 perf/x86/intel: Add Icelake support perf/x86/intel/uncore: Add Intel Icelake uncore support perf/x86/intel: Add Icelake desktop CPUID perf/x86/intel: Add more Icelake CPUIDs x86/cpu: Add Comet Lake to the Intel CPU models header perf/x86/intel: Add Comet Lake CPU support perf/x86/msr: Add Comet Lake CPU support perf/x86/cstate: Add Comet Lake CPU support perf/x86/msr: Add new CPU model numbers for Ice Lake perf/x86/cstate: Update C-state counters for Ice Lake Peter Zijlstra (1): perf/x86: Support constraint ranges Rajneesh Bhardwaj (1): perf/x86: Add Intel Ice Lake NNPI uncore support Stephane Eranian (1): perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking arch/x86/events/core.c | 15 + arch/x86/events/intel/core.c | 207 ++++++++++- arch/x86/events/intel/cstate.c | 41 ++- arch/x86/events/intel/ds.c | 505 ++++++++++++++++++++++---- arch/x86/events/intel/lbr.c | 35 +- arch/x86/events/intel/rapl.c | 1 + arch/x86/events/intel/uncore.c | 8 + arch/x86/events/intel/uncore.h | 1 + arch/x86/events/intel/uncore_snb.c | 91 +++++ arch/x86/events/msr.c | 5 + arch/x86/events/perf_event.h | 94 ++++- arch/x86/include/asm/cpu_device_id.h | 28 ++ arch/x86/include/asm/intel-family.h | 3 + arch/x86/include/asm/intel_ds.h | 2 +- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 50 ++- arch/x86/include/uapi/asm/perf_regs.h | 23 +- arch/x86/kernel/cpu/match.c | 31 ++ arch/x86/kernel/perf_regs.c | 27 +- 19 files changed, 1049 insertions(+), 119 deletions(-) Acked-by: Anthony Wong