mbox series

[SRU,D/OEM-OSP1-B,00/19] Add perf support for Comet Lake/Ice Lake CPU

Message ID 20191121081138.3436161-1-vicamo.yang@canonical.com
Headers show
Series Add perf support for Comet Lake/Ice Lake CPU | expand

Message

You-Sheng Yang Nov. 21, 2019, 8:11 a.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/1848978

[Impact]
There is no complete perf support for Comet Lake CPU. For Ice Lake, some
changes has been included in v5.3, but still misses CPU IDs.

[Fix]
perf support for Comet Lake is based on previous works for Ice Lake, so
changes for both have to be backported.

[Test Case]
On platforms with Comet Lake/Ice Lake CPUs, one should find new
cstate_pkg events c{8,9,10}-residency appear in output of `perf list`
for use.

[Regression Potential]
Low. This backports perf support for previously incompletedly supported
cpu models.

Andi Kleen (3):
  perf/x86/kvm: Avoid unnecessary work in guest filtering
  perf/x86/intel: Extract memory code PEBS parser for reuse
  perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them

Kan Liang (14):
  x86/cpufeature: Add facility to check for min microcode revisions
  perf/x86: Support outputting XMM registers
  perf/x86/intel/ds: Extract code of event update in short period
  perf/x86/intel: Support adaptive PEBS v4
  perf/x86/intel: Add Icelake support
  perf/x86/intel/uncore: Add Intel Icelake uncore support
  perf/x86/intel: Add Icelake desktop CPUID
  perf/x86/intel: Add more Icelake CPUIDs
  x86/cpu: Add Comet Lake to the Intel CPU models header
  perf/x86/intel: Add Comet Lake CPU support
  perf/x86/msr: Add Comet Lake CPU support
  perf/x86/cstate: Add Comet Lake CPU support
  perf/x86/msr: Add new CPU model numbers for Ice Lake
  perf/x86/cstate: Update C-state counters for Ice Lake

Peter Zijlstra (1):
  perf/x86: Support constraint ranges

Rajneesh Bhardwaj (1):
  perf/x86: Add Intel Ice Lake NNPI uncore support

 arch/x86/events/core.c                |  15 +
 arch/x86/events/intel/core.c          | 207 ++++++++++-
 arch/x86/events/intel/cstate.c        |  41 ++-
 arch/x86/events/intel/ds.c            | 505 ++++++++++++++++++++++----
 arch/x86/events/intel/lbr.c           |  35 +-
 arch/x86/events/intel/rapl.c          |   1 +
 arch/x86/events/intel/uncore.c        |   8 +
 arch/x86/events/intel/uncore.h        |   1 +
 arch/x86/events/intel/uncore_snb.c    |  91 +++++
 arch/x86/events/msr.c                 |   5 +
 arch/x86/events/perf_event.h          |  92 ++++-
 arch/x86/include/asm/cpu_device_id.h  |  28 ++
 arch/x86/include/asm/intel-family.h   |   3 +
 arch/x86/include/asm/intel_ds.h       |   2 +-
 arch/x86/include/asm/msr-index.h      |   1 +
 arch/x86/include/asm/perf_event.h     |  50 ++-
 arch/x86/include/uapi/asm/perf_regs.h |  23 +-
 arch/x86/kernel/cpu/match.c           |  31 ++
 arch/x86/kernel/perf_regs.c           |  27 +-
 19 files changed, 1048 insertions(+), 118 deletions(-)

Comments

You-Sheng Yang Nov. 27, 2019, 7:45 a.m. UTC | #1 
To SRU 6b89d4c1a to D/OEM-OSP1-B as well.

On 2019-11-21 16:11, You-Sheng Yang wrote:
> BugLink: https://bugs.launchpad.net/bugs/1848978
> 
> [Impact]
> There is no complete perf support for Comet Lake CPU. For Ice Lake, some
> changes has been included in v5.3, but still misses CPU IDs.
> 
> [Fix]
> perf support for Comet Lake is based on previous works for Ice Lake, so
> changes for both have to be backported.
> 
> [Test Case]
> On platforms with Comet Lake/Ice Lake CPUs, one should find new
> cstate_pkg events c{8,9,10}-residency appear in output of `perf list`
> for use.
> 
> [Regression Potential]
> Low. This backports perf support for previously incompletedly supported
> cpu models.
> 
> Andi Kleen (3):
>   perf/x86/kvm: Avoid unnecessary work in guest filtering
>   perf/x86/intel: Extract memory code PEBS parser for reuse
>   perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them
> 
> Kan Liang (14):
>   x86/cpufeature: Add facility to check for min microcode revisions
>   perf/x86: Support outputting XMM registers
>   perf/x86/intel/ds: Extract code of event update in short period
>   perf/x86/intel: Support adaptive PEBS v4
>   perf/x86/intel: Add Icelake support
>   perf/x86/intel/uncore: Add Intel Icelake uncore support
>   perf/x86/intel: Add Icelake desktop CPUID
>   perf/x86/intel: Add more Icelake CPUIDs
>   x86/cpu: Add Comet Lake to the Intel CPU models header
>   perf/x86/intel: Add Comet Lake CPU support
>   perf/x86/msr: Add Comet Lake CPU support
>   perf/x86/cstate: Add Comet Lake CPU support
>   perf/x86/msr: Add new CPU model numbers for Ice Lake
>   perf/x86/cstate: Update C-state counters for Ice Lake
> 
> Peter Zijlstra (1):
>   perf/x86: Support constraint ranges
> 
> Rajneesh Bhardwaj (1):
>   perf/x86: Add Intel Ice Lake NNPI uncore support
> 
>  arch/x86/events/core.c                |  15 +
>  arch/x86/events/intel/core.c          | 207 ++++++++++-
>  arch/x86/events/intel/cstate.c        |  41 ++-
>  arch/x86/events/intel/ds.c            | 505 ++++++++++++++++++++++----
>  arch/x86/events/intel/lbr.c           |  35 +-
>  arch/x86/events/intel/rapl.c          |   1 +
>  arch/x86/events/intel/uncore.c        |   8 +
>  arch/x86/events/intel/uncore.h        |   1 +
>  arch/x86/events/intel/uncore_snb.c    |  91 +++++
>  arch/x86/events/msr.c                 |   5 +
>  arch/x86/events/perf_event.h          |  92 ++++-
>  arch/x86/include/asm/cpu_device_id.h  |  28 ++
>  arch/x86/include/asm/intel-family.h   |   3 +
>  arch/x86/include/asm/intel_ds.h       |   2 +-
>  arch/x86/include/asm/msr-index.h      |   1 +
>  arch/x86/include/asm/perf_event.h     |  50 ++-
>  arch/x86/include/uapi/asm/perf_regs.h |  23 +-
>  arch/x86/kernel/cpu/match.c           |  31 ++
>  arch/x86/kernel/perf_regs.c           |  27 +-
>  19 files changed, 1048 insertions(+), 118 deletions(-)
>