From patchwork Thu Nov 15 02:08:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryder Lee X-Patchwork-Id: 998043 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42wQ6k38fMz9s47 for ; Thu, 15 Nov 2018 13:19:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2FD00C2219B; Thu, 15 Nov 2018 02:19:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.3 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RDNS_NONE, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 61627C224F6; Thu, 15 Nov 2018 02:08:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 42E1CC22471; Thu, 15 Nov 2018 02:08:43 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by lists.denx.de (Postfix) with ESMTPS id C9D4BC22495 for ; Thu, 15 Nov 2018 02:08:30 +0000 (UTC) X-UUID: 6499b305fa784b838c39e248b239e4e7-20181115 X-UUID: 6499b305fa784b838c39e248b239e4e7-20181115 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 742323500; Thu, 15 Nov 2018 10:08:23 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 15 Nov 2018 10:08:21 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 15 Nov 2018 10:08:21 +0800 From: Ryder Lee To: Tom Rini , Simon Glass , Albert Aribaud Date: Thu, 15 Nov 2018 10:08:02 +0800 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-SNTS-SMTP: 4323CEEE28312F7F5D7A42C19E92DF38CC7FACFF071093C19BCB153AB5089D932000:8 X-MTK: N Cc: Ryder Lee , Steven Liu , Roy Luo , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v5 14/18] serial: MediaTek: add high-speed uart driver for MediaTek SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Many SoCs from MediaTek have a high-speed uart. This UART is compatible with the ns16550 in legacy mode. It has extra registers for high-speed mode which can reach a maximum baudrate at 921600. However this UART will no longer be compatible if it's in high-speed mode. Some BootROM of MediaTek's SoCs will change the UART into high-speed mode and the U-Boot must use this driver to initialize the UART. Signed-off-by: Weijie Gao Tested-by: Ryder Lee Reviewed-by: Simon Glass --- Changes since v5: Add a specific driver for MTK UART Changes since v4: None --- drivers/serial/Kconfig | 20 ++++ drivers/serial/Makefile | 1 + drivers/serial/serial_mtk.c | 268 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/serial/serial_mtk.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 597db4b..7ab38b7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -368,6 +368,16 @@ config DEBUG_UART_OMAP You will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_MTK + bool "MediaTek High-speed UART" + depends on MTK_SERIAL + help + Select this to enable a debug UART using the MediaTek High-speed + UART driver. + You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + endchoice config DEBUG_UART_BASE @@ -692,6 +702,16 @@ config ZYNQ_SERIAL This driver supports the Cadence UART. It is found e.g. in Xilinx Zynq/ZynqMP. +config MTK_SERIAL + bool "MediaTek High-speed UART support" + depends on DM_SERIAL + help + Select this to enable UART support for MediaTek High-speed UART + devices. This driver uses driver model and requires a device + tree binding to operate. + The High-speed UART is compatible with the ns16550a UART and have + its own high-speed registers. + config MPC8XX_CONS bool "Console driver for MPC8XX" depends on MPC8xx diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 03dc29e..2f8d065 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o +obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c new file mode 100644 index 0000000..bce1be8 --- /dev/null +++ b/drivers/serial/serial_mtk.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek High-speed UART driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mtk_serial_regs { + u32 rbr; + u32 ier; + u32 fcr; + u32 lcr; + u32 mcr; + u32 lsr; + u32 msr; + u32 spr; + u32 mdr1; + u32 highspeed; + u32 sample_count; + u32 sample_point; + u32 fracdiv_l; + u32 fracdiv_m; + u32 escape_en; + u32 guard; + u32 rx_sel; +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ + +/* the data is correct if the real baud is within 3%. */ +#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) +#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100) + +struct mtk_serial_priv { + struct mtk_serial_regs __iomem *regs; + u32 clock; +}; + +static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud) +{ + bool support_clk12m_baud115200; + u32 quot, samplecount, realbaud; + + if ((baud <= 115200) && (priv->clock == 12000000)) + support_clk12m_baud115200 = true; + else + support_clk12m_baud115200 = false; + + if (baud <= 115200) { + writel(0, &priv->regs->highspeed); + quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud); + + if (support_clk12m_baud115200) { + writel(3, &priv->regs->highspeed); + quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud); + if (quot == 0) + quot = 1; + + samplecount = DIV_ROUND_CLOSEST(priv->clock, + quot * baud); + if (samplecount != 0) { + realbaud = priv->clock / samplecount / quot; + if ((realbaud > BAUD_ALLOW_MAX(baud)) || + (realbaud < BAUD_ALLOW_MIX(baud))) { + pr_info("baud %d can't be handled\n", + baud); + } + } else { + pr_info("samplecount is 0\n"); + } + } + } else if (baud <= 576000) { + writel(2, &priv->regs->highspeed); + + /* Set to next lower baudrate supported */ + if ((baud == 500000) || (baud == 576000)) + baud = 460800; + quot = DIV_ROUND_UP(priv->clock, 4 * baud); + } else { + writel(3, &priv->regs->highspeed); + quot = DIV_ROUND_UP(priv->clock, 256 * baud); + } + + /* set divisor */ + writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr); + writel(quot & 0xff, &priv->regs->dll); + writel((quot >> 8) & 0xff, &priv->regs->dlm); + writel(UART_LCR_WLS_8, &priv->regs->lcr); + + if (baud > 460800) { + u32 tmp; + + tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud); + writel(tmp - 1, &priv->regs->sample_count); + writel((tmp - 2) >> 1, &priv->regs->sample_point); + } else { + writel(0, &priv->regs->sample_count); + writel(0xff, &priv->regs->sample_point); + } + + if (support_clk12m_baud115200) { + writel(samplecount - 1, &priv->regs->sample_count); + writel((samplecount - 2) >> 1, &priv->regs->sample_point); + } +} + +static int mtk_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + _mtk_serial_setbrg(priv, baudrate); + + return 0; +} + +static int mtk_serial_putc(struct udevice *dev, const char ch) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->regs->lsr) & UART_LSR_THRE)) + return -EAGAIN; + + writel(ch, &priv->regs->thr); + + if (ch == '\n') + WATCHDOG_RESET(); + + return 0; +} + +static int mtk_serial_getc(struct udevice *dev) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->regs->lsr) & UART_LSR_DR)) + return -EAGAIN; + + return readl(&priv->regs->rbr); +} + +static int mtk_serial_pending(struct udevice *dev, bool input) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + if (input) + return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0; + else + return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; +} + +static int mtk_serial_probe(struct udevice *dev) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + /* Disable interrupt */ + writel(0, &priv->regs->ier); + + return 0; +} + +static int mtk_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + struct clk clk; + int err; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, 0, MAP_NOCACHE); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + priv->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("mtk_serial: failed to get clock\n"); + return err; + } + + if (!priv->clock) + priv->clock = dev_read_u32_default(dev, "clock-frequency", 0); + + if (!priv->clock) { + debug("mtk_serial: clock not defined\n"); + return -EINVAL; + } + + return 0; +} + +static const struct dm_serial_ops mtk_serial_ops = { + .putc = mtk_serial_putc, + .pending = mtk_serial_pending, + .getc = mtk_serial_getc, + .setbrg = mtk_serial_setbrg, +}; + +static const struct udevice_id mtk_serial_ids[] = { + { .compatible = "mediatek,hsuart" }, + { .compatible = "mediatek,mt6577-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_mtk) = { + .name = "serial_mtk", + .id = UCLASS_SERIAL, + .of_match = mtk_serial_ids, + .ofdata_to_platdata = mtk_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct mtk_serial_priv), + .probe = mtk_serial_probe, + .ops = &mtk_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_MTK + +#include + +static inline void _debug_uart_init(void) +{ + struct mtk_serial_priv priv; + + priv.regs = (void *) CONFIG_DEBUG_UART_BASE; + priv.clock = CONFIG_DEBUG_UART_CLOCK; + + writel(0, &priv.regs->ier); + + _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + struct mtk_serial_regs __iomem *regs = + (void *) CONFIG_DEBUG_UART_BASE; + + while (!(readl(®s->lsr) & UART_LSR_THRE)) + ; + + writel(ch, ®s->thr); +} + +DEBUG_UART_FUNCS + +#endif \ No newline at end of file