From patchwork Tue Oct 2 06:13:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryder Lee X-Patchwork-Id: 977708 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Pbrd2n5cz9sj9 for ; Tue, 2 Oct 2018 21:04:32 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 4241FC22011; Tue, 2 Oct 2018 11:02:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.3 required=5.0 tests=RDNS_NONE, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BA0A3C2203A; Tue, 2 Oct 2018 10:59:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 84502C21FBB; Tue, 2 Oct 2018 06:14:13 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by lists.denx.de (Postfix) with ESMTPS id 05720C21FB7 for ; Tue, 2 Oct 2018 06:14:11 +0000 (UTC) X-UUID: 58c6f23a0cb44cccbfef7f6230125902-20181002 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1986679671; Tue, 02 Oct 2018 14:14:04 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 2 Oct 2018 14:14:02 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 2 Oct 2018 14:14:03 +0800 From: Ryder Lee To: Tom Rini , Simon Glass , Albert Aribaud Date: Tue, 2 Oct 2018 14:13:47 +0800 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Tue, 02 Oct 2018 10:59:23 +0000 Cc: Steven Liu , Roy Luo , Sean Wang , Weijie Gao , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 10/20] timer: MediaTek: add timer driver for MediaTek SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds clock source/event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee --- drivers/timer/Kconfig | 7 ++++ drivers/timer/Makefile | 1 + drivers/timer/mtk_timer.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 drivers/timer/mtk_timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a7d600b..83ec0e6 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -147,4 +147,11 @@ config MPC83XX_TIMER Select this to enable support for the timer found on devices based on the MPC83xx family of SoCs. +config MTK_TIMER + bool "MediaTek timer support" + depends on TIMER + help + Select this to enable support for the timer found on + MediaTek devices. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 7f19c49..c4fbab2 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o +obj-$(CONFIG_MTK_TIMER) += mtk_timer.o diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c new file mode 100644 index 0000000..b5e76bd --- /dev/null +++ b/drivers/timer/mtk_timer.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek timer driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include + +#define MTK_GPT4_CTRL 0x40 +#define MTK_GPT4_CLK 0x44 +#define MTK_GPT4_CNT 0x48 + +#define GPT4_ENABLE BIT(0) +#define GPT4_CLEAR BIT(1) +#define GPT4_FREERUN GENMASK(5, 4) +#define GPT4_CLK_SYS 0x0 +#define GPT4_CLK_DIV1 0x0 + +struct mtk_timer_priv { + void __iomem *base; +}; + +static int mtk_timer_get_count(struct udevice *dev, u64 *count) +{ + struct mtk_timer_priv *priv = dev_get_priv(dev); + u32 val = readl(priv->base + MTK_GPT4_CNT); + + *count = timer_conv_64(val); + + return 0; +} + +static int mtk_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mtk_timer_priv *priv = dev_get_priv(dev); + struct clk clk, parent; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &parent); + if (!ret) { + ret = clk_set_parent(&clk, &parent); + if (ret) + return ret; + } + + uc_priv->clock_rate = clk_get_rate(&clk); + if (!uc_priv->clock_rate) + return -EINVAL; + + return 0; +} + +static const struct timer_ops mtk_timer_ops = { + .get_count = mtk_timer_get_count, +}; + +static const struct udevice_id mtk_timer_ids[] = { + { .compatible = "mediatek,timer" }, + { } +}; + +U_BOOT_DRIVER(mtk_timer) = { + .name = "mtk_timer", + .id = UCLASS_TIMER, + .of_match = mtk_timer_ids, + .priv_auto_alloc_size = sizeof(struct mtk_timer_priv), + .probe = mtk_timer_probe, + .ops = &mtk_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +};